183b40c31SHolger Brunck /*
283b40c31SHolger Brunck  * (C) Copyright 2009
383b40c31SHolger Brunck  * Marvell Semiconductor <www.marvell.com>
483b40c31SHolger Brunck  * Prafulla Wadaskar <prafulla@marvell.com>
583b40c31SHolger Brunck  *
683b40c31SHolger Brunck  * (C) Copyright 2009
783b40c31SHolger Brunck  * Stefan Roese, DENX Software Engineering, sr@denx.de.
883b40c31SHolger Brunck  *
98170aefcSHolger Brunck  * (C) Copyright 2011-2012
108170aefcSHolger Brunck  * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
118170aefcSHolger Brunck  * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
1283b40c31SHolger Brunck  *
1383b40c31SHolger Brunck  * See file CREDITS for list of people who contributed to this
1483b40c31SHolger Brunck  * project.
1583b40c31SHolger Brunck  *
1683b40c31SHolger Brunck  * This program is free software; you can redistribute it and/or
1783b40c31SHolger Brunck  * modify it under the terms of the GNU General Public License as
1883b40c31SHolger Brunck  * published by the Free Software Foundation; either version 2 of
1983b40c31SHolger Brunck  * the License, or (at your option) any later version.
2083b40c31SHolger Brunck  *
2183b40c31SHolger Brunck  * This program is distributed in the hope that it will be useful,
2283b40c31SHolger Brunck  * but WITHOUT ANY WARRANTY; without even the implied warranty of
2383b40c31SHolger Brunck  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
2483b40c31SHolger Brunck  * GNU General Public License for more details.
2583b40c31SHolger Brunck  *
2683b40c31SHolger Brunck  * You should have received a copy of the GNU General Public License
2783b40c31SHolger Brunck  * along with this program; if not, write to the Free Software
2883b40c31SHolger Brunck  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
2983b40c31SHolger Brunck  * MA 02110-1301 USA
3083b40c31SHolger Brunck  */
3183b40c31SHolger Brunck 
3283b40c31SHolger Brunck /*
3383b40c31SHolger Brunck  * for linking errors see
3483b40c31SHolger Brunck  * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
3583b40c31SHolger Brunck  */
3683b40c31SHolger Brunck 
3783b40c31SHolger Brunck #ifndef _CONFIG_KM_KIRKWOOD_H
3883b40c31SHolger Brunck #define _CONFIG_KM_KIRKWOOD_H
3983b40c31SHolger Brunck 
4048ced62cSHolger Brunck /* KM_KIRKWOOD */
41e29c6d04SHolger Brunck #if defined(CONFIG_KM_KIRKWOOD)
4283b40c31SHolger Brunck #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
43d9354530SHolger Brunck #define CONFIG_HOSTNAME			km_kirkwood
4448ced62cSHolger Brunck #define CONFIG_KM_DISABLE_PCIE
458170aefcSHolger Brunck #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
4648ced62cSHolger Brunck 
4748ced62cSHolger Brunck /* KM_KIRKWOOD_PCI */
48e29c6d04SHolger Brunck #elif defined(CONFIG_KM_KIRKWOOD_PCI)
4983b40c31SHolger Brunck #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
50d9354530SHolger Brunck #define CONFIG_HOSTNAME			km_kirkwood_pci
518170aefcSHolger Brunck #define KM_IVM_BUS			"pca9544a:70:9"	/* I2C2 (Mux-Port 1)*/
5248ced62cSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
5348ced62cSHolger Brunck 
548170aefcSHolger Brunck /* KM_NUSA */
558170aefcSHolger Brunck #elif defined(CONFIG_KM_NUSA)
568170aefcSHolger Brunck #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
578170aefcSHolger Brunck #define CONFIG_IDENT_STRING		"\nKeymile NUSA"
58d9354530SHolger Brunck #define CONFIG_HOSTNAME			kmnusa
598170aefcSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
608170aefcSHolger Brunck #define CONFIG_SYS_KWD_CONFIG \
618170aefcSHolger Brunck 		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
628170aefcSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
638170aefcSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
648170aefcSHolger Brunck #define CONFIG_KM_PIGGY4_88E6352
65be3e8be0SValentin Longchamp #define CONFIG_MV88E6352_SWITCH
66be3e8be0SValentin Longchamp #define CONFIG_KM_MVEXTSW_ADDR		0x10
678170aefcSHolger Brunck 
68f945439aSHolger Brunck /* KM_MGCOGE3UN */
69f945439aSHolger Brunck #elif defined(CONFIG_KM_MGCOGE3UN)
70f945439aSHolger Brunck #define CONFIG_IDENT_STRING		"\nKeymile COGE3UN"
71f945439aSHolger Brunck #define CONFIG_HOSTNAME			mgcoge3un
72f945439aSHolger Brunck #define KM_IVM_BUS			"pca9547:70:9" /* I2C2 (Mux-Port 1)*/
73f945439aSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
74f945439aSHolger Brunck #define CONFIG_SYS_KWD_CONFIG \
75f945439aSHolger Brunck 		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
76f945439aSHolger Brunck #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
77f945439aSHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
78f945439aSHolger Brunck #define CONFIG_KM_DISABLE_PCIE
79f945439aSHolger Brunck #define CONFIG_KM_PIGGY4_88E6061
80f945439aSHolger Brunck 
81f945439aSHolger Brunck /* KMCOGE5UN */
82d9354530SHolger Brunck #elif defined(CONFIG_KM_COGE5UN)
83d9354530SHolger Brunck #define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
84d9354530SHolger Brunck #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
85d9354530SHolger Brunck #undef	CONFIG_SYS_KWD_CONFIG
86d9354530SHolger Brunck #define CONFIG_SYS_KWD_CONFIG \
87d9354530SHolger Brunck 		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
88d9354530SHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
89d9354530SHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
90d9354530SHolger Brunck #define CONFIG_HOSTNAME			kmcoge5un
91d9354530SHolger Brunck #define CONFIG_KM_DISABLE_PCIE
92d9354530SHolger Brunck #define CONFIG_KM_PIGGY4_88E6352
936ef64861SHolger Brunck 
946ef64861SHolger Brunck /* KM_PORTL2 */
956ef64861SHolger Brunck #elif defined(CONFIG_KM_PORTL2)
966ef64861SHolger Brunck #define CONFIG_IDENT_STRING		"\nKeymile Port-L2"
976ef64861SHolger Brunck #define CONFIG_HOSTNAME			portl2
986ef64861SHolger Brunck #define KM_IVM_BUS			"pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
996ef64861SHolger Brunck #define CONFIG_KM_PIGGY4_88E6061
1006ef64861SHolger Brunck 
101*90639feaSHolger Brunck /* KM_SUV31 */
102*90639feaSHolger Brunck #elif defined(CONFIG_KM_SUV31)
103*90639feaSHolger Brunck #define KM_IVM_BUS			"pca9547:70:9"	/* I2C2 (Mux-Port 1)*/
104*90639feaSHolger Brunck #define CONFIG_IDENT_STRING		"\nKeymile SUV31"
105*90639feaSHolger Brunck #define CONFIG_HOSTNAME			kmsuv31
106*90639feaSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
107*90639feaSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
108*90639feaSHolger Brunck 
1098170aefcSHolger Brunck #else
1108170aefcSHolger Brunck #error ("Board unsupported")
11183b40c31SHolger Brunck #endif
11283b40c31SHolger Brunck 
1138170aefcSHolger Brunck /* include common defines/options for all arm based Keymile boards */
1148170aefcSHolger Brunck #include "km/km_arm.h"
1158170aefcSHolger Brunck 
1168170aefcSHolger Brunck #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
11783b40c31SHolger Brunck #define KM_ENV_BUS	"pca9544a:70:d"	/* I2C2 (Mux-Port 5)*/
1188170aefcSHolger Brunck #endif
1198170aefcSHolger Brunck 
1208170aefcSHolger Brunck #if defined(CONFIG_KM_PIGGY4_88E6352)
1218170aefcSHolger Brunck /*
1228170aefcSHolger Brunck  * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
1238170aefcSHolger Brunck  * an Marvell 88E6352 simple switch.
1248170aefcSHolger Brunck  * In this case we have to change the default settings for the etherent mac.
1258170aefcSHolger Brunck  * There is NO ethernet phy. The ARM and Switch are conencted directly over
1268170aefcSHolger Brunck  * RGMII in MAC-MAC mode
1278170aefcSHolger Brunck  * In this case 1GBit full duplex and autoneg off
1288170aefcSHolger Brunck  */
1298170aefcSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE		( \
1308170aefcSHolger Brunck 	MVGBE_FORCE_LINK_PASS			    | \
1318170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
1328170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
1338170aefcSHolger Brunck 	MVGBE_ADV_NO_FLOW_CTRL			    | \
1348170aefcSHolger Brunck 	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
1358170aefcSHolger Brunck 	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
1368170aefcSHolger Brunck 	(1 << 9) /* Reserved bit has to be 1 */	| \
1378170aefcSHolger Brunck 	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
1388170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
1398170aefcSHolger Brunck 	MVGBE_DTE_ADV_0				        | \
1408170aefcSHolger Brunck 	MVGBE_MIIPHY_MAC_MODE			    | \
1418170aefcSHolger Brunck 	MVGBE_AUTO_NEG_NO_CHANGE		    | \
1428170aefcSHolger Brunck 	MVGBE_MAX_RX_PACKET_1552BYTE		| \
1438170aefcSHolger Brunck 	MVGBE_CLR_EXT_LOOPBACK			    | \
1448170aefcSHolger Brunck 	MVGBE_SET_FULL_DUPLEX_MODE		    | \
1458170aefcSHolger Brunck 	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
1468170aefcSHolger Brunck 	MVGBE_SET_GMII_SPEED_TO_1000	    |\
1478170aefcSHolger Brunck 	MVGBE_SET_MII_SPEED_TO_100)
1488170aefcSHolger Brunck 
1498170aefcSHolger Brunck #endif
15083b40c31SHolger Brunck 
151f945439aSHolger Brunck #ifdef CONFIG_KM_PIGGY4_88E6061
152f945439aSHolger Brunck /*
153f945439aSHolger Brunck  * Some keymile boards like mgcoge3un have their PIGGY4 connected via
154f945439aSHolger Brunck  * an Marvell 88E6061 simple switch.
155f945439aSHolger Brunck  * In this case we have to change the default settings for the
156f945439aSHolger Brunck  * ethernet phy connected to the kirkwood.
157f945439aSHolger Brunck  * In this case 100MB full duplex and autoneg off
158f945439aSHolger Brunck  */
159f945439aSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE		( \
160f945439aSHolger Brunck 	MVGBE_FORCE_LINK_PASS			| \
161f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
162f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
163f945439aSHolger Brunck 	MVGBE_ADV_NO_FLOW_CTRL			| \
164f945439aSHolger Brunck 	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
165f945439aSHolger Brunck 	MVGBE_FORCE_BP_MODE_NO_JAM		| \
166f945439aSHolger Brunck 	(1 << 9) /* Reserved bit has to be 1 */	| \
167f945439aSHolger Brunck 	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
168f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
169f945439aSHolger Brunck 	MVGBE_DTE_ADV_0				| \
170f945439aSHolger Brunck 	MVGBE_MIIPHY_MAC_MODE			| \
171f945439aSHolger Brunck 	MVGBE_AUTO_NEG_NO_CHANGE		| \
172f945439aSHolger Brunck 	MVGBE_MAX_RX_PACKET_1552BYTE		| \
173f945439aSHolger Brunck 	MVGBE_CLR_EXT_LOOPBACK			| \
174f945439aSHolger Brunck 	MVGBE_SET_FULL_DUPLEX_MODE		| \
175f945439aSHolger Brunck 	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
176f945439aSHolger Brunck 	MVGBE_SET_GMII_SPEED_TO_10_100	|\
177f945439aSHolger Brunck 	MVGBE_SET_MII_SPEED_TO_100)
178f945439aSHolger Brunck #endif
179f945439aSHolger Brunck 
180f945439aSHolger Brunck #ifdef CONFIG_KM_DISABLE_PCI
181f945439aSHolger Brunck #undef  CONFIG_KIRKWOOD_PCIE_INIT
182f945439aSHolger Brunck #endif
183b37f7724SValentin Longchamp 
184b37f7724SValentin Longchamp 
18583b40c31SHolger Brunck #endif /* _CONFIG_KM_KIRKWOOD */
186