183b40c31SHolger Brunck /* 283b40c31SHolger Brunck * (C) Copyright 2009 383b40c31SHolger Brunck * Marvell Semiconductor <www.marvell.com> 483b40c31SHolger Brunck * Prafulla Wadaskar <prafulla@marvell.com> 583b40c31SHolger Brunck * 683b40c31SHolger Brunck * (C) Copyright 2009 783b40c31SHolger Brunck * Stefan Roese, DENX Software Engineering, sr@denx.de. 883b40c31SHolger Brunck * 98170aefcSHolger Brunck * (C) Copyright 2011-2012 108170aefcSHolger Brunck * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com 118170aefcSHolger Brunck * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 1283b40c31SHolger Brunck * 131a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1483b40c31SHolger Brunck */ 1583b40c31SHolger Brunck 1683b40c31SHolger Brunck /* 1783b40c31SHolger Brunck * for linking errors see 1883b40c31SHolger Brunck * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html 1983b40c31SHolger Brunck */ 2083b40c31SHolger Brunck 2183b40c31SHolger Brunck #ifndef _CONFIG_KM_KIRKWOOD_H 2283b40c31SHolger Brunck #define _CONFIG_KM_KIRKWOOD_H 2383b40c31SHolger Brunck 2448ced62cSHolger Brunck /* KM_KIRKWOOD */ 25e29c6d04SHolger Brunck #if defined(CONFIG_KM_KIRKWOOD) 2683b40c31SHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" 27d9354530SHolger Brunck #define CONFIG_HOSTNAME km_kirkwood 2848ced62cSHolger Brunck #define CONFIG_KM_DISABLE_PCIE 29f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 3048ced62cSHolger Brunck 3148ced62cSHolger Brunck /* KM_KIRKWOOD_PCI */ 32e29c6d04SHolger Brunck #elif defined(CONFIG_KM_KIRKWOOD_PCI) 3383b40c31SHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" 34d9354530SHolger Brunck #define CONFIG_HOSTNAME km_kirkwood_pci 35f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 3648ced62cSHolger Brunck #define CONFIG_KM_FPGA_CONFIG 3748ced62cSHolger Brunck 38*5e4eeab9SKarlheinz Jerg /* KM_KIRKWOOD_128M16 */ 39*5e4eeab9SKarlheinz Jerg #elif defined(CONFIG_KM_KIRKWOOD_128M16) 40*5e4eeab9SKarlheinz Jerg #define CONFIG_IDENT_STRING "\nKeymile Kirkwood 128M16" 41*5e4eeab9SKarlheinz Jerg #define CONFIG_HOSTNAME km_kirkwood_128m16 42*5e4eeab9SKarlheinz Jerg #undef CONFIG_SYS_KWD_CONFIG 43*5e4eeab9SKarlheinz Jerg #define CONFIG_SYS_KWD_CONFIG \ 44*5e4eeab9SKarlheinz Jerg $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 45*5e4eeab9SKarlheinz Jerg #define CONFIG_KM_DISABLE_PCIE 46*5e4eeab9SKarlheinz Jerg #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ 47*5e4eeab9SKarlheinz Jerg 488170aefcSHolger Brunck /* KM_NUSA */ 498170aefcSHolger Brunck #elif defined(CONFIG_KM_NUSA) 50f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 518170aefcSHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile NUSA" 52d9354530SHolger Brunck #define CONFIG_HOSTNAME kmnusa 538170aefcSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG 548170aefcSHolger Brunck #define CONFIG_SYS_KWD_CONFIG \ 558170aefcSHolger Brunck $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 568170aefcSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR 578170aefcSHolger Brunck #define CONFIG_KM_FPGA_CONFIG 588170aefcSHolger Brunck #define CONFIG_KM_PIGGY4_88E6352 59be3e8be0SValentin Longchamp #define CONFIG_MV88E6352_SWITCH 60be3e8be0SValentin Longchamp #define CONFIG_KM_MVEXTSW_ADDR 0x10 618170aefcSHolger Brunck 62f945439aSHolger Brunck /* KM_MGCOGE3UN */ 63f945439aSHolger Brunck #elif defined(CONFIG_KM_MGCOGE3UN) 64f945439aSHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile COGE3UN" 65f945439aSHolger Brunck #define CONFIG_HOSTNAME mgcoge3un 66f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 67f945439aSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG 68f945439aSHolger Brunck #define CONFIG_SYS_KWD_CONFIG \ 69f945439aSHolger Brunck $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg 70f945439aSHolger Brunck #define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" 71f945439aSHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 72f945439aSHolger Brunck #define CONFIG_KM_DISABLE_PCIE 73f945439aSHolger Brunck #define CONFIG_KM_PIGGY4_88E6061 74f945439aSHolger Brunck 75f945439aSHolger Brunck /* KMCOGE5UN */ 76d9354530SHolger Brunck #elif defined(CONFIG_KM_COGE5UN) 77d9354530SHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile COGE5UN" 78f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 79d9354530SHolger Brunck #undef CONFIG_SYS_KWD_CONFIG 80d9354530SHolger Brunck #define CONFIG_SYS_KWD_CONFIG \ 81d9354530SHolger Brunck $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg 82d9354530SHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR 83d9354530SHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 84d9354530SHolger Brunck #define CONFIG_HOSTNAME kmcoge5un 85d9354530SHolger Brunck #define CONFIG_KM_DISABLE_PCIE 86d9354530SHolger Brunck #define CONFIG_KM_PIGGY4_88E6352 876ef64861SHolger Brunck 886ef64861SHolger Brunck /* KM_PORTL2 */ 896ef64861SHolger Brunck #elif defined(CONFIG_KM_PORTL2) 906ef64861SHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile Port-L2" 916ef64861SHolger Brunck #define CONFIG_HOSTNAME portl2 92f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 936ef64861SHolger Brunck #define CONFIG_KM_PIGGY4_88E6061 946ef64861SHolger Brunck 9590639feaSHolger Brunck /* KM_SUV31 */ 9690639feaSHolger Brunck #elif defined(CONFIG_KM_SUV31) 97ea818dbbSHeiko Schocher #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 9890639feaSHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile SUV31" 9990639feaSHolger Brunck #define CONFIG_HOSTNAME kmsuv31 10090639feaSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR 10190639feaSHolger Brunck #define CONFIG_KM_FPGA_CONFIG 10290639feaSHolger Brunck 1038170aefcSHolger Brunck #else 1048170aefcSHolger Brunck #error ("Board unsupported") 10583b40c31SHolger Brunck #endif 10683b40c31SHolger Brunck 1078170aefcSHolger Brunck /* include common defines/options for all arm based Keymile boards */ 1088170aefcSHolger Brunck #include "km/km_arm.h" 1098170aefcSHolger Brunck 1108170aefcSHolger Brunck #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR 111ea818dbbSHeiko Schocher #define KM_ENV_BUS 5 /* I2C2 (Mux-Port 5)*/ 1128170aefcSHolger Brunck #endif 1138170aefcSHolger Brunck 1148170aefcSHolger Brunck #if defined(CONFIG_KM_PIGGY4_88E6352) 1158170aefcSHolger Brunck /* 1168170aefcSHolger Brunck * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via 1178170aefcSHolger Brunck * an Marvell 88E6352 simple switch. 1188170aefcSHolger Brunck * In this case we have to change the default settings for the etherent mac. 1198170aefcSHolger Brunck * There is NO ethernet phy. The ARM and Switch are conencted directly over 1208170aefcSHolger Brunck * RGMII in MAC-MAC mode 1218170aefcSHolger Brunck * In this case 1GBit full duplex and autoneg off 1228170aefcSHolger Brunck */ 1238170aefcSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE ( \ 1248170aefcSHolger Brunck MVGBE_FORCE_LINK_PASS | \ 1258170aefcSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 1268170aefcSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 1278170aefcSHolger Brunck MVGBE_ADV_NO_FLOW_CTRL | \ 1288170aefcSHolger Brunck MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 1298170aefcSHolger Brunck MVGBE_FORCE_BP_MODE_NO_JAM | \ 1308170aefcSHolger Brunck (1 << 9) /* Reserved bit has to be 1 */ | \ 1318170aefcSHolger Brunck MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 1328170aefcSHolger Brunck MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 1338170aefcSHolger Brunck MVGBE_DTE_ADV_0 | \ 1348170aefcSHolger Brunck MVGBE_MIIPHY_MAC_MODE | \ 1358170aefcSHolger Brunck MVGBE_AUTO_NEG_NO_CHANGE | \ 1368170aefcSHolger Brunck MVGBE_MAX_RX_PACKET_1552BYTE | \ 1378170aefcSHolger Brunck MVGBE_CLR_EXT_LOOPBACK | \ 1388170aefcSHolger Brunck MVGBE_SET_FULL_DUPLEX_MODE | \ 1398170aefcSHolger Brunck MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 1408170aefcSHolger Brunck MVGBE_SET_GMII_SPEED_TO_1000 |\ 1418170aefcSHolger Brunck MVGBE_SET_MII_SPEED_TO_100) 1428170aefcSHolger Brunck 1438170aefcSHolger Brunck #endif 14483b40c31SHolger Brunck 145f945439aSHolger Brunck #ifdef CONFIG_KM_PIGGY4_88E6061 146f945439aSHolger Brunck /* 147f945439aSHolger Brunck * Some keymile boards like mgcoge3un have their PIGGY4 connected via 148f945439aSHolger Brunck * an Marvell 88E6061 simple switch. 149f945439aSHolger Brunck * In this case we have to change the default settings for the 150f945439aSHolger Brunck * ethernet phy connected to the kirkwood. 151f945439aSHolger Brunck * In this case 100MB full duplex and autoneg off 152f945439aSHolger Brunck */ 153f945439aSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE ( \ 154f945439aSHolger Brunck MVGBE_FORCE_LINK_PASS | \ 155f945439aSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 156f945439aSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 157f945439aSHolger Brunck MVGBE_ADV_NO_FLOW_CTRL | \ 158f945439aSHolger Brunck MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 159f945439aSHolger Brunck MVGBE_FORCE_BP_MODE_NO_JAM | \ 160f945439aSHolger Brunck (1 << 9) /* Reserved bit has to be 1 */ | \ 161f945439aSHolger Brunck MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 162f945439aSHolger Brunck MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 163f945439aSHolger Brunck MVGBE_DTE_ADV_0 | \ 164f945439aSHolger Brunck MVGBE_MIIPHY_MAC_MODE | \ 165f945439aSHolger Brunck MVGBE_AUTO_NEG_NO_CHANGE | \ 166f945439aSHolger Brunck MVGBE_MAX_RX_PACKET_1552BYTE | \ 167f945439aSHolger Brunck MVGBE_CLR_EXT_LOOPBACK | \ 168f945439aSHolger Brunck MVGBE_SET_FULL_DUPLEX_MODE | \ 169f945439aSHolger Brunck MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 170f945439aSHolger Brunck MVGBE_SET_GMII_SPEED_TO_10_100 |\ 171f945439aSHolger Brunck MVGBE_SET_MII_SPEED_TO_100) 172f945439aSHolger Brunck #endif 173f945439aSHolger Brunck 174f945439aSHolger Brunck #ifdef CONFIG_KM_DISABLE_PCI 175f945439aSHolger Brunck #undef CONFIG_KIRKWOOD_PCIE_INIT 176f945439aSHolger Brunck #endif 177b37f7724SValentin Longchamp 178b37f7724SValentin Longchamp 17983b40c31SHolger Brunck #endif /* _CONFIG_KM_KIRKWOOD */ 180