183b40c31SHolger Brunck /*
283b40c31SHolger Brunck  * (C) Copyright 2009
383b40c31SHolger Brunck  * Marvell Semiconductor <www.marvell.com>
483b40c31SHolger Brunck  * Prafulla Wadaskar <prafulla@marvell.com>
583b40c31SHolger Brunck  *
683b40c31SHolger Brunck  * (C) Copyright 2009
783b40c31SHolger Brunck  * Stefan Roese, DENX Software Engineering, sr@denx.de.
883b40c31SHolger Brunck  *
98170aefcSHolger Brunck  * (C) Copyright 2011-2012
108170aefcSHolger Brunck  * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
118170aefcSHolger Brunck  * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
1283b40c31SHolger Brunck  *
131a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
1483b40c31SHolger Brunck  */
1583b40c31SHolger Brunck 
1683b40c31SHolger Brunck /*
1783b40c31SHolger Brunck  * for linking errors see
1883b40c31SHolger Brunck  * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
1983b40c31SHolger Brunck  */
2083b40c31SHolger Brunck 
2183b40c31SHolger Brunck #ifndef _CONFIG_KM_KIRKWOOD_H
2283b40c31SHolger Brunck #define _CONFIG_KM_KIRKWOOD_H
2383b40c31SHolger Brunck 
2448ced62cSHolger Brunck /* KM_KIRKWOOD */
25e29c6d04SHolger Brunck #if defined(CONFIG_KM_KIRKWOOD)
26*5bc0543dSMario Six #define CONFIG_HOSTNAME			"km_kirkwood"
2748ced62cSHolger Brunck #define CONFIG_KM_DISABLE_PCIE
28f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
2948ced62cSHolger Brunck 
3048ced62cSHolger Brunck /* KM_KIRKWOOD_PCI */
31e29c6d04SHolger Brunck #elif defined(CONFIG_KM_KIRKWOOD_PCI)
32*5bc0543dSMario Six #define CONFIG_HOSTNAME			"km_kirkwood_pci"
33f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
3448ced62cSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
3558c90c88SHolger Brunck #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
3658c90c88SHolger Brunck #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
3748ced62cSHolger Brunck 
385e4eeab9SKarlheinz Jerg /* KM_KIRKWOOD_128M16 */
395e4eeab9SKarlheinz Jerg #elif defined(CONFIG_KM_KIRKWOOD_128M16)
40*5bc0543dSMario Six #define CONFIG_HOSTNAME			"km_kirkwood_128m16"
415e4eeab9SKarlheinz Jerg #undef CONFIG_SYS_KWD_CONFIG
424ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
435e4eeab9SKarlheinz Jerg #define CONFIG_KM_DISABLE_PCIE
44e28d4a27SHolger Brunck #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
455e4eeab9SKarlheinz Jerg 
469c134e18SGerlando Falauto /* KM_NUSA / KM_SUGP1 */
479c134e18SGerlando Falauto #elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
48f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
499c134e18SGerlando Falauto 
509c134e18SGerlando Falauto # if defined(CONFIG_KM_NUSA)
51*5bc0543dSMario Six #define CONFIG_HOSTNAME			"kmnusa"
529c134e18SGerlando Falauto # elif defined(CONFIG_KM_SUGP1)
53*5bc0543dSMario Six #define CONFIG_HOSTNAME			"kmsugp1"
549c134e18SGerlando Falauto #define KM_PCIE_RESET_MPP7
559c134e18SGerlando Falauto #endif
569c134e18SGerlando Falauto 
578170aefcSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
584ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
598170aefcSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
608170aefcSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
618170aefcSHolger Brunck #define CONFIG_KM_PIGGY4_88E6352
62be3e8be0SValentin Longchamp #define CONFIG_MV88E6352_SWITCH
63be3e8be0SValentin Longchamp #define CONFIG_KM_MVEXTSW_ADDR		0x10
648170aefcSHolger Brunck 
65f945439aSHolger Brunck /* KM_MGCOGE3UN */
66f945439aSHolger Brunck #elif defined(CONFIG_KM_MGCOGE3UN)
67*5bc0543dSMario Six #define CONFIG_HOSTNAME			"mgcoge3un"
68f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
69f945439aSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
704ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
71f945439aSHolger Brunck #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
72f945439aSHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
73f945439aSHolger Brunck #define CONFIG_KM_DISABLE_PCIE
74f945439aSHolger Brunck #define CONFIG_KM_PIGGY4_88E6061
75f945439aSHolger Brunck 
76f945439aSHolger Brunck /* KMCOGE5UN */
77d9354530SHolger Brunck #elif defined(CONFIG_KM_COGE5UN)
78f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
79d9354530SHolger Brunck #undef	CONFIG_SYS_KWD_CONFIG
804ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
81d9354530SHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
82d9354530SHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
83*5bc0543dSMario Six #define CONFIG_HOSTNAME			"kmcoge5un"
84d9354530SHolger Brunck #define CONFIG_KM_DISABLE_PCIE
85d9354530SHolger Brunck #define CONFIG_KM_PIGGY4_88E6352
866ef64861SHolger Brunck 
876ef64861SHolger Brunck /* KM_PORTL2 */
886ef64861SHolger Brunck #elif defined(CONFIG_KM_PORTL2)
89*5bc0543dSMario Six #define CONFIG_HOSTNAME			"portl2"
90f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
916ef64861SHolger Brunck #define CONFIG_KM_PIGGY4_88E6061
926ef64861SHolger Brunck 
9390639feaSHolger Brunck /* KM_SUV31 */
9490639feaSHolger Brunck #elif defined(CONFIG_KM_SUV31)
95ea818dbbSHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
96*5bc0543dSMario Six #define CONFIG_HOSTNAME			"kmsuv31"
972a4ebef2SHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
984ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
9990639feaSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
10090639feaSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
10158c90c88SHolger Brunck #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
10258c90c88SHolger Brunck #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
1038170aefcSHolger Brunck #else
1048170aefcSHolger Brunck #error ("Board unsupported")
10583b40c31SHolger Brunck #endif
10683b40c31SHolger Brunck 
1078170aefcSHolger Brunck /* include common defines/options for all arm based Keymile boards */
1088170aefcSHolger Brunck #include "km/km_arm.h"
1098170aefcSHolger Brunck 
1108170aefcSHolger Brunck #if defined(CONFIG_KM_PIGGY4_88E6352)
1118170aefcSHolger Brunck /*
1128170aefcSHolger Brunck  * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
1138170aefcSHolger Brunck  * an Marvell 88E6352 simple switch.
1148170aefcSHolger Brunck  * In this case we have to change the default settings for the etherent mac.
1158170aefcSHolger Brunck  * There is NO ethernet phy. The ARM and Switch are conencted directly over
1168170aefcSHolger Brunck  * RGMII in MAC-MAC mode
1178170aefcSHolger Brunck  * In this case 1GBit full duplex and autoneg off
1188170aefcSHolger Brunck  */
1198170aefcSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE		( \
1208170aefcSHolger Brunck 	MVGBE_FORCE_LINK_PASS			    | \
1218170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
1228170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
1238170aefcSHolger Brunck 	MVGBE_ADV_NO_FLOW_CTRL			    | \
1248170aefcSHolger Brunck 	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
1258170aefcSHolger Brunck 	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
1268170aefcSHolger Brunck 	(1 << 9) /* Reserved bit has to be 1 */	| \
1278170aefcSHolger Brunck 	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
1288170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
1298170aefcSHolger Brunck 	MVGBE_DTE_ADV_0				        | \
1308170aefcSHolger Brunck 	MVGBE_MIIPHY_MAC_MODE			    | \
1318170aefcSHolger Brunck 	MVGBE_AUTO_NEG_NO_CHANGE		    | \
1328170aefcSHolger Brunck 	MVGBE_MAX_RX_PACKET_1552BYTE		| \
1338170aefcSHolger Brunck 	MVGBE_CLR_EXT_LOOPBACK			    | \
1348170aefcSHolger Brunck 	MVGBE_SET_FULL_DUPLEX_MODE		    | \
1358170aefcSHolger Brunck 	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
1368170aefcSHolger Brunck 	MVGBE_SET_GMII_SPEED_TO_1000	    |\
1378170aefcSHolger Brunck 	MVGBE_SET_MII_SPEED_TO_100)
1388170aefcSHolger Brunck 
1398170aefcSHolger Brunck #endif
14083b40c31SHolger Brunck 
141f945439aSHolger Brunck #ifdef CONFIG_KM_PIGGY4_88E6061
142f945439aSHolger Brunck /*
143f945439aSHolger Brunck  * Some keymile boards like mgcoge3un have their PIGGY4 connected via
144f945439aSHolger Brunck  * an Marvell 88E6061 simple switch.
145f945439aSHolger Brunck  * In this case we have to change the default settings for the
146f945439aSHolger Brunck  * ethernet phy connected to the kirkwood.
147f945439aSHolger Brunck  * In this case 100MB full duplex and autoneg off
148f945439aSHolger Brunck  */
149f945439aSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE		( \
150f945439aSHolger Brunck 	MVGBE_FORCE_LINK_PASS			| \
151f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
152f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
153f945439aSHolger Brunck 	MVGBE_ADV_NO_FLOW_CTRL			| \
154f945439aSHolger Brunck 	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
155f945439aSHolger Brunck 	MVGBE_FORCE_BP_MODE_NO_JAM		| \
156f945439aSHolger Brunck 	(1 << 9) /* Reserved bit has to be 1 */	| \
157f945439aSHolger Brunck 	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
158f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
159f945439aSHolger Brunck 	MVGBE_DTE_ADV_0				| \
160f945439aSHolger Brunck 	MVGBE_MIIPHY_MAC_MODE			| \
161f945439aSHolger Brunck 	MVGBE_AUTO_NEG_NO_CHANGE		| \
162f945439aSHolger Brunck 	MVGBE_MAX_RX_PACKET_1552BYTE		| \
163f945439aSHolger Brunck 	MVGBE_CLR_EXT_LOOPBACK			| \
164f945439aSHolger Brunck 	MVGBE_SET_FULL_DUPLEX_MODE		| \
165f945439aSHolger Brunck 	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
166f945439aSHolger Brunck 	MVGBE_SET_GMII_SPEED_TO_10_100	|\
167f945439aSHolger Brunck 	MVGBE_SET_MII_SPEED_TO_100)
168f945439aSHolger Brunck #endif
169f945439aSHolger Brunck 
170f945439aSHolger Brunck #ifdef CONFIG_KM_DISABLE_PCI
171f945439aSHolger Brunck #undef  CONFIG_KIRKWOOD_PCIE_INIT
172f945439aSHolger Brunck #endif
173b37f7724SValentin Longchamp 
17483b40c31SHolger Brunck #endif /* _CONFIG_KM_KIRKWOOD */
175