1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
283b40c31SHolger Brunck /*
383b40c31SHolger Brunck  * (C) Copyright 2009
483b40c31SHolger Brunck  * Marvell Semiconductor <www.marvell.com>
583b40c31SHolger Brunck  * Prafulla Wadaskar <prafulla@marvell.com>
683b40c31SHolger Brunck  *
783b40c31SHolger Brunck  * (C) Copyright 2009
883b40c31SHolger Brunck  * Stefan Roese, DENX Software Engineering, sr@denx.de.
983b40c31SHolger Brunck  *
108170aefcSHolger Brunck  * (C) Copyright 2011-2012
118170aefcSHolger Brunck  * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
128170aefcSHolger Brunck  * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
1383b40c31SHolger Brunck  */
1483b40c31SHolger Brunck 
1583b40c31SHolger Brunck /*
1683b40c31SHolger Brunck  * for linking errors see
1783b40c31SHolger Brunck  * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
1883b40c31SHolger Brunck  */
1983b40c31SHolger Brunck 
2083b40c31SHolger Brunck #ifndef _CONFIG_KM_KIRKWOOD_H
2183b40c31SHolger Brunck #define _CONFIG_KM_KIRKWOOD_H
2283b40c31SHolger Brunck 
2348ced62cSHolger Brunck /* KM_KIRKWOOD */
24e29c6d04SHolger Brunck #if defined(CONFIG_KM_KIRKWOOD)
255bc0543dSMario Six #define CONFIG_HOSTNAME			"km_kirkwood"
2648ced62cSHolger Brunck #define CONFIG_KM_DISABLE_PCIE
27f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
2848ced62cSHolger Brunck 
2948ced62cSHolger Brunck /* KM_KIRKWOOD_PCI */
30e29c6d04SHolger Brunck #elif defined(CONFIG_KM_KIRKWOOD_PCI)
315bc0543dSMario Six #define CONFIG_HOSTNAME			"km_kirkwood_pci"
32f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
3348ced62cSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
3458c90c88SHolger Brunck #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
3558c90c88SHolger Brunck #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
3648ced62cSHolger Brunck 
375e4eeab9SKarlheinz Jerg /* KM_KIRKWOOD_128M16 */
385e4eeab9SKarlheinz Jerg #elif defined(CONFIG_KM_KIRKWOOD_128M16)
395bc0543dSMario Six #define CONFIG_HOSTNAME			"km_kirkwood_128m16"
405e4eeab9SKarlheinz Jerg #undef CONFIG_SYS_KWD_CONFIG
414ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
425e4eeab9SKarlheinz Jerg #define CONFIG_KM_DISABLE_PCIE
43e28d4a27SHolger Brunck #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
445e4eeab9SKarlheinz Jerg 
459c134e18SGerlando Falauto /* KM_NUSA / KM_SUGP1 */
469c134e18SGerlando Falauto #elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
47f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
489c134e18SGerlando Falauto 
499c134e18SGerlando Falauto # if defined(CONFIG_KM_NUSA)
505bc0543dSMario Six #define CONFIG_HOSTNAME			"kmnusa"
519c134e18SGerlando Falauto # elif defined(CONFIG_KM_SUGP1)
525bc0543dSMario Six #define CONFIG_HOSTNAME			"kmsugp1"
539c134e18SGerlando Falauto #define KM_PCIE_RESET_MPP7
549c134e18SGerlando Falauto #endif
559c134e18SGerlando Falauto 
568170aefcSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
574ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
588170aefcSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
598170aefcSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
608170aefcSHolger Brunck #define CONFIG_KM_PIGGY4_88E6352
61be3e8be0SValentin Longchamp #define CONFIG_MV88E6352_SWITCH
62be3e8be0SValentin Longchamp #define CONFIG_KM_MVEXTSW_ADDR		0x10
638170aefcSHolger Brunck 
64f945439aSHolger Brunck /* KM_MGCOGE3UN */
65f945439aSHolger Brunck #elif defined(CONFIG_KM_MGCOGE3UN)
665bc0543dSMario Six #define CONFIG_HOSTNAME			"mgcoge3un"
67f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
68f945439aSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
694ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
70f945439aSHolger Brunck #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
71f945439aSHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
72f945439aSHolger Brunck #define CONFIG_KM_DISABLE_PCIE
73f945439aSHolger Brunck #define CONFIG_KM_PIGGY4_88E6061
74f945439aSHolger Brunck 
75f945439aSHolger Brunck /* KMCOGE5UN */
76d9354530SHolger Brunck #elif defined(CONFIG_KM_COGE5UN)
77f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
78d9354530SHolger Brunck #undef	CONFIG_SYS_KWD_CONFIG
794ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
80d9354530SHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
81d9354530SHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
825bc0543dSMario Six #define CONFIG_HOSTNAME			"kmcoge5un"
83d9354530SHolger Brunck #define CONFIG_KM_DISABLE_PCIE
84d9354530SHolger Brunck #define CONFIG_KM_PIGGY4_88E6352
856ef64861SHolger Brunck 
866ef64861SHolger Brunck /* KM_PORTL2 */
876ef64861SHolger Brunck #elif defined(CONFIG_KM_PORTL2)
885bc0543dSMario Six #define CONFIG_HOSTNAME			"portl2"
89f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
906ef64861SHolger Brunck #define CONFIG_KM_PIGGY4_88E6061
916ef64861SHolger Brunck 
9290639feaSHolger Brunck /* KM_SUV31 */
9390639feaSHolger Brunck #elif defined(CONFIG_KM_SUV31)
94ea818dbbSHeiko Schocher #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
955bc0543dSMario Six #define CONFIG_HOSTNAME			"kmsuv31"
962a4ebef2SHolger Brunck #undef CONFIG_SYS_KWD_CONFIG
974ab3fc5eSMasahiro Yamada #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
9890639feaSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR
9990639feaSHolger Brunck #define CONFIG_KM_FPGA_CONFIG
10058c90c88SHolger Brunck #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
10158c90c88SHolger Brunck #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
1028170aefcSHolger Brunck #else
1038170aefcSHolger Brunck #error ("Board unsupported")
10483b40c31SHolger Brunck #endif
10583b40c31SHolger Brunck 
1068170aefcSHolger Brunck /* include common defines/options for all arm based Keymile boards */
1078170aefcSHolger Brunck #include "km/km_arm.h"
1088170aefcSHolger Brunck 
1098170aefcSHolger Brunck #if defined(CONFIG_KM_PIGGY4_88E6352)
1108170aefcSHolger Brunck /*
1118170aefcSHolger Brunck  * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
1128170aefcSHolger Brunck  * an Marvell 88E6352 simple switch.
1138170aefcSHolger Brunck  * In this case we have to change the default settings for the etherent mac.
1148170aefcSHolger Brunck  * There is NO ethernet phy. The ARM and Switch are conencted directly over
1158170aefcSHolger Brunck  * RGMII in MAC-MAC mode
1168170aefcSHolger Brunck  * In this case 1GBit full duplex and autoneg off
1178170aefcSHolger Brunck  */
1188170aefcSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE		( \
1198170aefcSHolger Brunck 	MVGBE_FORCE_LINK_PASS			    | \
1208170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
1218170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
1228170aefcSHolger Brunck 	MVGBE_ADV_NO_FLOW_CTRL			    | \
1238170aefcSHolger Brunck 	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
1248170aefcSHolger Brunck 	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
1258170aefcSHolger Brunck 	(1 << 9) /* Reserved bit has to be 1 */	| \
1268170aefcSHolger Brunck 	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
1278170aefcSHolger Brunck 	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
1288170aefcSHolger Brunck 	MVGBE_DTE_ADV_0				        | \
1298170aefcSHolger Brunck 	MVGBE_MIIPHY_MAC_MODE			    | \
1308170aefcSHolger Brunck 	MVGBE_AUTO_NEG_NO_CHANGE		    | \
1318170aefcSHolger Brunck 	MVGBE_MAX_RX_PACKET_1552BYTE		| \
1328170aefcSHolger Brunck 	MVGBE_CLR_EXT_LOOPBACK			    | \
1338170aefcSHolger Brunck 	MVGBE_SET_FULL_DUPLEX_MODE		    | \
1348170aefcSHolger Brunck 	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
1358170aefcSHolger Brunck 	MVGBE_SET_GMII_SPEED_TO_1000	    |\
1368170aefcSHolger Brunck 	MVGBE_SET_MII_SPEED_TO_100)
1378170aefcSHolger Brunck 
1388170aefcSHolger Brunck #endif
13983b40c31SHolger Brunck 
140f945439aSHolger Brunck #ifdef CONFIG_KM_PIGGY4_88E6061
141f945439aSHolger Brunck /*
142f945439aSHolger Brunck  * Some keymile boards like mgcoge3un have their PIGGY4 connected via
143f945439aSHolger Brunck  * an Marvell 88E6061 simple switch.
144f945439aSHolger Brunck  * In this case we have to change the default settings for the
145f945439aSHolger Brunck  * ethernet phy connected to the kirkwood.
146f945439aSHolger Brunck  * In this case 100MB full duplex and autoneg off
147f945439aSHolger Brunck  */
148f945439aSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE		( \
149f945439aSHolger Brunck 	MVGBE_FORCE_LINK_PASS			| \
150f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
151f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
152f945439aSHolger Brunck 	MVGBE_ADV_NO_FLOW_CTRL			| \
153f945439aSHolger Brunck 	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
154f945439aSHolger Brunck 	MVGBE_FORCE_BP_MODE_NO_JAM		| \
155f945439aSHolger Brunck 	(1 << 9) /* Reserved bit has to be 1 */	| \
156f945439aSHolger Brunck 	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
157f945439aSHolger Brunck 	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
158f945439aSHolger Brunck 	MVGBE_DTE_ADV_0				| \
159f945439aSHolger Brunck 	MVGBE_MIIPHY_MAC_MODE			| \
160f945439aSHolger Brunck 	MVGBE_AUTO_NEG_NO_CHANGE		| \
161f945439aSHolger Brunck 	MVGBE_MAX_RX_PACKET_1552BYTE		| \
162f945439aSHolger Brunck 	MVGBE_CLR_EXT_LOOPBACK			| \
163f945439aSHolger Brunck 	MVGBE_SET_FULL_DUPLEX_MODE		| \
164f945439aSHolger Brunck 	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
165f945439aSHolger Brunck 	MVGBE_SET_GMII_SPEED_TO_10_100	|\
166f945439aSHolger Brunck 	MVGBE_SET_MII_SPEED_TO_100)
167f945439aSHolger Brunck #endif
168f945439aSHolger Brunck 
169f945439aSHolger Brunck #ifdef CONFIG_KM_DISABLE_PCI
170f945439aSHolger Brunck #undef  CONFIG_KIRKWOOD_PCIE_INIT
171f945439aSHolger Brunck #endif
172b37f7724SValentin Longchamp 
17383b40c31SHolger Brunck #endif /* _CONFIG_KM_KIRKWOOD */
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