1 /* 2 * (C) Copyright 2012 3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com> 4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* KMBEC FPGA (PRIO) */ 13 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 14 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 15 16 #if defined CONFIG_KMETER1 17 #define CONFIG_HOSTNAME kmeter1 18 #define CONFIG_KM_BOARD_NAME "kmeter1" 19 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" 20 #elif defined CONFIG_KMCOGE5NE 21 #define CONFIG_HOSTNAME kmcoge5ne 22 #define CONFIG_KM_BOARD_NAME "kmcoge5ne" 23 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" 24 #define CONFIG_NAND_ECC_BCH 25 #define CONFIG_NAND_KMETER1 26 #define CONFIG_SYS_MAX_NAND_DEVICE 1 27 #define NAND_MAX_CHIPS 1 28 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ 29 30 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" 31 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" 32 #define MTDIDS_DEFAULT "nor0=boot,nand0=app" 33 34 #define MTDPARTS_DEFAULT "mtdparts=" \ 35 "boot:" \ 36 "768k(u-boot)," \ 37 "128k(env)," \ 38 "128k(envred)," \ 39 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \ 40 "app:" \ 41 "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");" 42 #else 43 #error ("Board not supported") 44 #endif 45 46 /* 47 * High Level Configuration Options 48 */ 49 #define CONFIG_QE /* Has QE */ 50 #define CONFIG_MPC8360 /* MPC8360 CPU specific */ 51 52 #define CONFIG_SYS_TEXT_BASE 0xF0000000 53 54 /* include common defines/options for all 83xx Keymile boards */ 55 #include "km/km83xx-common.h" 56 57 /* 58 * System IO Setup 59 */ 60 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) 61 62 /* 63 * Hardware Reset Configuration Word 64 */ 65 #define CONFIG_SYS_HRCW_LOW (\ 66 HRCWL_CSB_TO_CLKIN_4X1 | \ 67 HRCWL_CORE_TO_CSB_2X1 | \ 68 HRCWL_CE_PLL_VCO_DIV_2 | \ 69 HRCWL_CE_TO_PLL_1X6) 70 71 #define CONFIG_SYS_HRCW_HIGH (\ 72 HRCWH_CORE_ENABLE | \ 73 HRCWH_FROM_0X00000100 | \ 74 HRCWH_BOOTSEQ_DISABLE | \ 75 HRCWH_SW_WATCHDOG_DISABLE | \ 76 HRCWH_ROM_LOC_LOCAL_16BIT | \ 77 HRCWH_BIG_ENDIAN | \ 78 HRCWH_LALE_EARLY | \ 79 HRCWH_LDP_CLEAR) 80 81 /** 82 * DDR RAM settings 83 */ 84 #define CONFIG_SYS_DDR_SDRAM_CFG (\ 85 SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 86 SDRAM_CFG_SREN | \ 87 SDRAM_CFG_HSE) 88 89 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 90 91 #ifdef CONFIG_KMCOGE5NE 92 /** 93 * KMCOGE5NE has 512 MB RAM 94 */ 95 #define CONFIG_SYS_DDR_CS0_CONFIG (\ 96 CSCONFIG_EN | \ 97 CSCONFIG_AP | \ 98 CSCONFIG_ODT_WR_ONLY_CURRENT | \ 99 CSCONFIG_BANK_BIT_3 | \ 100 CSCONFIG_ROW_BIT_13 | \ 101 CSCONFIG_COL_BIT_10) 102 #else 103 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 104 CSCONFIG_ROW_BIT_13 | \ 105 CSCONFIG_COL_BIT_10 | \ 106 CSCONFIG_ODT_WR_ONLY_CURRENT) 107 #endif 108 109 #define CONFIG_SYS_DDR_CLK_CNTL (\ 110 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 111 112 #define CONFIG_SYS_DDR_INTERVAL (\ 113 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 114 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) 115 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 117 118 #define CONFIG_SYS_DDRCDR (\ 119 DDRCDR_EN | \ 120 DDRCDR_Q_DRN) 121 #define CONFIG_SYS_DDR_MODE 0x47860452 122 #define CONFIG_SYS_DDR_MODE2 0x8080c000 123 124 #define CONFIG_SYS_DDR_TIMING_0 (\ 125 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 126 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 127 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 128 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 129 (0 << TIMING_CFG0_WWT_SHIFT) | \ 130 (0 << TIMING_CFG0_RRT_SHIFT) | \ 131 (0 << TIMING_CFG0_WRT_SHIFT) | \ 132 (0 << TIMING_CFG0_RWT_SHIFT)) 133 134 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ 135 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 136 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 137 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 138 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 139 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 140 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 141 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 142 143 #define CONFIG_SYS_DDR_TIMING_2 (\ 144 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 145 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 146 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 147 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 148 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 149 (5 << TIMING_CFG2_CPO_SHIFT) | \ 150 (0 << TIMING_CFG2_ADD_LAT_SHIFT)) 151 152 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 153 154 /* EEprom support */ 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 156 157 /* 158 * Local Bus Configuration & Clock Setup 159 */ 160 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 161 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 162 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 163 164 /* 165 * PAXE on the local bus CS3 166 */ 167 #define CONFIG_SYS_PAXE_BASE 0xA0000000 168 #define CONFIG_SYS_PAXE_SIZE 256 169 170 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE 171 172 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ 173 174 #define CONFIG_SYS_BR3_PRELIM (\ 175 CONFIG_SYS_PAXE_BASE | \ 176 (1 << BR_PS_SHIFT) | \ 177 BR_V) 178 179 #define CONFIG_SYS_OR3_PRELIM (\ 180 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ 181 OR_GPCM_CSNT | \ 182 OR_GPCM_ACS_DIV2 | \ 183 OR_GPCM_SCY_2 | \ 184 OR_GPCM_TRLX | \ 185 OR_GPCM_EAD) 186 187 #ifdef CONFIG_KMCOGE5NE 188 /* 189 * BFTIC3 on the local bus CS4 190 */ 191 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 192 #define CONFIG_SYS_BFTIC3_SIZE 256 193 194 #define CONFIG_SYS_BR4_PRELIM (\ 195 CONFIG_SYS_BFTIC3_BASE |\ 196 (1 << BR_PS_SHIFT) | \ 197 BR_V) 198 199 #define CONFIG_SYS_OR4_PRELIM (\ 200 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\ 201 OR_GPCM_CSNT | \ 202 OR_GPCM_ACS_DIV2 |\ 203 OR_GPCM_SCY_2 |\ 204 OR_GPCM_TRLX |\ 205 OR_GPCM_EAD) 206 #endif 207 208 /* 209 * MMU Setup 210 */ 211 212 /* PAXE: icache cacheable, but dcache-inhibit and guarded */ 213 #define CONFIG_SYS_IBAT5L (\ 214 CONFIG_SYS_PAXE_BASE | \ 215 BATL_PP_10 | \ 216 BATL_MEMCOHERENCE) 217 218 #define CONFIG_SYS_IBAT5U (\ 219 CONFIG_SYS_PAXE_BASE | \ 220 BATU_BL_256M | \ 221 BATU_VS | \ 222 BATU_VP) 223 224 #define CONFIG_SYS_DBAT5L (\ 225 CONFIG_SYS_PAXE_BASE | \ 226 BATL_PP_10 | \ 227 BATL_CACHEINHIBIT | \ 228 BATL_GUARDEDSTORAGE) 229 230 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 231 232 #ifdef CONFIG_KMCOGE5NE 233 /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ 234 #define CONFIG_SYS_IBAT6L (\ 235 CONFIG_SYS_BFTIC3_BASE | \ 236 BATL_PP_10 | \ 237 BATL_MEMCOHERENCE) 238 239 #define CONFIG_SYS_IBAT6U (\ 240 CONFIG_SYS_BFTIC3_BASE | \ 241 BATU_BL_256M | \ 242 BATU_VS | \ 243 BATU_VP) 244 245 #define CONFIG_SYS_DBAT6L (\ 246 CONFIG_SYS_BFTIC3_BASE | \ 247 BATL_PP_10 | \ 248 BATL_CACHEINHIBIT | \ 249 BATL_GUARDEDSTORAGE) 250 251 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 252 253 /* DDR/LBC SDRAM next 256M: cacheable */ 254 #define CONFIG_SYS_IBAT7L (\ 255 CONFIG_SYS_SDRAM_BASE2 |\ 256 BATL_PP_10 |\ 257 BATL_CACHEINHIBIT |\ 258 BATL_GUARDEDSTORAGE) 259 260 #define CONFIG_SYS_IBAT7U (\ 261 CONFIG_SYS_SDRAM_BASE2 |\ 262 BATU_BL_256M |\ 263 BATU_VS |\ 264 BATU_VP) 265 /* enable POST tests */ 266 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) 267 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ 268 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END 269 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ 270 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ 271 272 #else 273 #define CONFIG_SYS_IBAT6L (0) 274 #define CONFIG_SYS_IBAT6U (0) 275 #define CONFIG_SYS_IBAT7L (0) 276 #define CONFIG_SYS_IBAT7U (0) 277 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 278 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 279 #endif 280 281 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 282 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 283 284 #endif /* CONFIG */ 285