1 /* 2 * (C) Copyright 2012 3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com> 4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* KMBEC FPGA (PRIO) */ 13 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 14 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 15 16 #if defined CONFIG_KMETER1 17 #define CONFIG_HOSTNAME kmeter1 18 #define CONFIG_KM_BOARD_NAME "kmeter1" 19 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" 20 #elif defined CONFIG_KMCOGE5NE 21 #define CONFIG_HOSTNAME kmcoge5ne 22 #define CONFIG_KM_BOARD_NAME "kmcoge5ne" 23 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" 24 #define CONFIG_NAND_ECC_BCH 25 #define CONFIG_BCH 26 #define CONFIG_NAND_KMETER1 27 #define CONFIG_SYS_MAX_NAND_DEVICE 1 28 #define NAND_MAX_CHIPS 1 29 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ 30 31 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" 32 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" 33 #define MTDIDS_DEFAULT "nor0=boot,nand0=app" 34 35 #define MTDPARTS_DEFAULT "mtdparts=" \ 36 "boot:" \ 37 "768k(u-boot)," \ 38 "128k(env)," \ 39 "128k(envred)," \ 40 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \ 41 "app:" \ 42 "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");" 43 #else 44 #error ("Board not supported") 45 #endif 46 47 /* 48 * High Level Configuration Options 49 */ 50 #define CONFIG_QE /* Has QE */ 51 #define CONFIG_MPC8360 /* MPC8360 CPU specific */ 52 53 #define CONFIG_SYS_TEXT_BASE 0xF0000000 54 55 /* include common defines/options for all 83xx Keymile boards */ 56 #include "km/km83xx-common.h" 57 58 /* 59 * System IO Setup 60 */ 61 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) 62 63 /* 64 * Hardware Reset Configuration Word 65 */ 66 #define CONFIG_SYS_HRCW_LOW (\ 67 HRCWL_CSB_TO_CLKIN_4X1 | \ 68 HRCWL_CORE_TO_CSB_2X1 | \ 69 HRCWL_CE_PLL_VCO_DIV_2 | \ 70 HRCWL_CE_TO_PLL_1X6) 71 72 #define CONFIG_SYS_HRCW_HIGH (\ 73 HRCWH_CORE_ENABLE | \ 74 HRCWH_FROM_0X00000100 | \ 75 HRCWH_BOOTSEQ_DISABLE | \ 76 HRCWH_SW_WATCHDOG_DISABLE | \ 77 HRCWH_ROM_LOC_LOCAL_16BIT | \ 78 HRCWH_BIG_ENDIAN | \ 79 HRCWH_LALE_EARLY | \ 80 HRCWH_LDP_CLEAR) 81 82 /** 83 * DDR RAM settings 84 */ 85 #define CONFIG_SYS_DDR_SDRAM_CFG (\ 86 SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 87 SDRAM_CFG_SREN | \ 88 SDRAM_CFG_HSE) 89 90 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 91 92 #ifdef CONFIG_KMCOGE5NE 93 /** 94 * KMCOGE5NE has 512 MB RAM 95 */ 96 #define CONFIG_SYS_DDR_CS0_CONFIG (\ 97 CSCONFIG_EN | \ 98 CSCONFIG_AP | \ 99 CSCONFIG_ODT_WR_ONLY_CURRENT | \ 100 CSCONFIG_BANK_BIT_3 | \ 101 CSCONFIG_ROW_BIT_13 | \ 102 CSCONFIG_COL_BIT_10) 103 #else 104 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 105 CSCONFIG_ROW_BIT_13 | \ 106 CSCONFIG_COL_BIT_10 | \ 107 CSCONFIG_ODT_WR_ONLY_CURRENT) 108 #endif 109 110 #define CONFIG_SYS_DDR_CLK_CNTL (\ 111 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 112 113 #define CONFIG_SYS_DDR_INTERVAL (\ 114 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 115 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) 116 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 118 119 #define CONFIG_SYS_DDRCDR (\ 120 DDRCDR_EN | \ 121 DDRCDR_Q_DRN) 122 #define CONFIG_SYS_DDR_MODE 0x47860452 123 #define CONFIG_SYS_DDR_MODE2 0x8080c000 124 125 #define CONFIG_SYS_DDR_TIMING_0 (\ 126 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 127 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 128 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 129 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 130 (0 << TIMING_CFG0_WWT_SHIFT) | \ 131 (0 << TIMING_CFG0_RRT_SHIFT) | \ 132 (0 << TIMING_CFG0_WRT_SHIFT) | \ 133 (0 << TIMING_CFG0_RWT_SHIFT)) 134 135 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ 136 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 137 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 138 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 139 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 140 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 141 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 142 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 143 144 #define CONFIG_SYS_DDR_TIMING_2 (\ 145 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 146 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 147 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 148 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 149 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 150 (5 << TIMING_CFG2_CPO_SHIFT) | \ 151 (0 << TIMING_CFG2_ADD_LAT_SHIFT)) 152 153 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 154 155 /* EEprom support */ 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 157 158 /* 159 * Local Bus Configuration & Clock Setup 160 */ 161 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 162 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 163 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 164 165 /* 166 * PAXE on the local bus CS3 167 */ 168 #define CONFIG_SYS_PAXE_BASE 0xA0000000 169 #define CONFIG_SYS_PAXE_SIZE 256 170 171 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE 172 173 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ 174 175 #define CONFIG_SYS_BR3_PRELIM (\ 176 CONFIG_SYS_PAXE_BASE | \ 177 (1 << BR_PS_SHIFT) | \ 178 BR_V) 179 180 #define CONFIG_SYS_OR3_PRELIM (\ 181 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ 182 OR_GPCM_CSNT | \ 183 OR_GPCM_ACS_DIV2 | \ 184 OR_GPCM_SCY_2 | \ 185 OR_GPCM_TRLX | \ 186 OR_GPCM_EAD) 187 188 #ifdef CONFIG_KMCOGE5NE 189 /* 190 * BFTIC3 on the local bus CS4 191 */ 192 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 193 #define CONFIG_SYS_BFTIC3_SIZE 256 194 195 #define CONFIG_SYS_BR4_PRELIM (\ 196 CONFIG_SYS_BFTIC3_BASE |\ 197 (1 << BR_PS_SHIFT) | \ 198 BR_V) 199 200 #define CONFIG_SYS_OR4_PRELIM (\ 201 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\ 202 OR_GPCM_CSNT | \ 203 OR_GPCM_ACS_DIV2 |\ 204 OR_GPCM_SCY_2 |\ 205 OR_GPCM_TRLX |\ 206 OR_GPCM_EAD) 207 #endif 208 209 /* 210 * MMU Setup 211 */ 212 213 /* PAXE: icache cacheable, but dcache-inhibit and guarded */ 214 #define CONFIG_SYS_IBAT5L (\ 215 CONFIG_SYS_PAXE_BASE | \ 216 BATL_PP_10 | \ 217 BATL_MEMCOHERENCE) 218 219 #define CONFIG_SYS_IBAT5U (\ 220 CONFIG_SYS_PAXE_BASE | \ 221 BATU_BL_256M | \ 222 BATU_VS | \ 223 BATU_VP) 224 225 #define CONFIG_SYS_DBAT5L (\ 226 CONFIG_SYS_PAXE_BASE | \ 227 BATL_PP_10 | \ 228 BATL_CACHEINHIBIT | \ 229 BATL_GUARDEDSTORAGE) 230 231 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 232 233 #ifdef CONFIG_KMCOGE5NE 234 /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ 235 #define CONFIG_SYS_IBAT6L (\ 236 CONFIG_SYS_BFTIC3_BASE | \ 237 BATL_PP_10 | \ 238 BATL_MEMCOHERENCE) 239 240 #define CONFIG_SYS_IBAT6U (\ 241 CONFIG_SYS_BFTIC3_BASE | \ 242 BATU_BL_256M | \ 243 BATU_VS | \ 244 BATU_VP) 245 246 #define CONFIG_SYS_DBAT6L (\ 247 CONFIG_SYS_BFTIC3_BASE | \ 248 BATL_PP_10 | \ 249 BATL_CACHEINHIBIT | \ 250 BATL_GUARDEDSTORAGE) 251 252 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 253 254 /* DDR/LBC SDRAM next 256M: cacheable */ 255 #define CONFIG_SYS_IBAT7L (\ 256 CONFIG_SYS_SDRAM_BASE2 |\ 257 BATL_PP_10 |\ 258 BATL_CACHEINHIBIT |\ 259 BATL_GUARDEDSTORAGE) 260 261 #define CONFIG_SYS_IBAT7U (\ 262 CONFIG_SYS_SDRAM_BASE2 |\ 263 BATU_BL_256M |\ 264 BATU_VS |\ 265 BATU_VP) 266 /* enable POST tests */ 267 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) 268 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ 269 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END 270 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ 271 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ 272 273 #else 274 #define CONFIG_SYS_IBAT6L (0) 275 #define CONFIG_SYS_IBAT6U (0) 276 #define CONFIG_SYS_IBAT7L (0) 277 #define CONFIG_SYS_IBAT7U (0) 278 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 279 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 280 #endif 281 282 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 283 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 284 285 #endif /* CONFIG */ 286