1 /* 2 * (C) Copyright 2012 3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com> 4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* KMBEC FPGA (PRIO) */ 16 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 17 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 18 19 #if defined CONFIG_KMETER1 20 #define CONFIG_HOSTNAME kmeter1 21 #define CONFIG_KM_BOARD_NAME "kmeter1" 22 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" 23 #elif defined CONFIG_KMCOGE5NE 24 #define CONFIG_HOSTNAME kmcoge5ne 25 #define CONFIG_KM_BOARD_NAME "kmcoge5ne" 26 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" 27 #define CONFIG_CMD_NAND 28 #define CONFIG_NAND_KMETER1 29 #define CONFIG_SYS_MAX_NAND_DEVICE 1 30 #define NAND_MAX_CHIPS 1 31 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ 32 33 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" 34 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" 35 #define MTDIDS_DEFAULT "nor0=boot,nand0=app" 36 37 #define MTDPARTS_DEFAULT "mtdparts=" \ 38 "boot:" \ 39 "768k(u-boot)," \ 40 "128k(env)," \ 41 "128k(envred)," \ 42 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \ 43 "app:" \ 44 "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");" 45 #else 46 #error ("Board not supported") 47 #endif 48 49 /* 50 * High Level Configuration Options 51 */ 52 #define CONFIG_QE /* Has QE */ 53 #define CONFIG_MPC8360 /* MPC8360 CPU specific */ 54 55 #define CONFIG_SYS_TEXT_BASE 0xF0000000 56 57 /* include common defines/options for all 83xx Keymile boards */ 58 #include "km/km83xx-common.h" 59 60 /* 61 * System IO Setup 62 */ 63 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) 64 65 /* 66 * Hardware Reset Configuration Word 67 */ 68 #define CONFIG_SYS_HRCW_LOW (\ 69 HRCWL_CSB_TO_CLKIN_4X1 | \ 70 HRCWL_CORE_TO_CSB_2X1 | \ 71 HRCWL_CE_PLL_VCO_DIV_2 | \ 72 HRCWL_CE_TO_PLL_1X6) 73 74 #define CONFIG_SYS_HRCW_HIGH (\ 75 HRCWH_CORE_ENABLE | \ 76 HRCWH_FROM_0X00000100 | \ 77 HRCWH_BOOTSEQ_DISABLE | \ 78 HRCWH_SW_WATCHDOG_DISABLE | \ 79 HRCWH_ROM_LOC_LOCAL_16BIT | \ 80 HRCWH_BIG_ENDIAN | \ 81 HRCWH_LALE_EARLY | \ 82 HRCWH_LDP_CLEAR) 83 84 /** 85 * DDR RAM settings 86 */ 87 #define CONFIG_SYS_DDR_SDRAM_CFG (\ 88 SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 89 SDRAM_CFG_SREN | \ 90 SDRAM_CFG_HSE) 91 92 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 93 94 #ifdef CONFIG_KMCOGE5NE 95 /** 96 * KMCOGE5NE has 512 MB RAM 97 */ 98 #define CONFIG_SYS_DDR_CS0_CONFIG (\ 99 CSCONFIG_EN | \ 100 CSCONFIG_AP | \ 101 CSCONFIG_ODT_RD_ONLY_CURRENT | \ 102 CSCONFIG_BANK_BIT_3 | \ 103 CSCONFIG_ROW_BIT_13 | \ 104 CSCONFIG_COL_BIT_10) 105 #else 106 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 107 CSCONFIG_ROW_BIT_13 | \ 108 CSCONFIG_COL_BIT_10 | \ 109 CSCONFIG_ODT_RD_ONLY_CURRENT) 110 #endif 111 112 #define CONFIG_SYS_DDR_CLK_CNTL (\ 113 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 114 115 #define CONFIG_SYS_DDR_INTERVAL (\ 116 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 117 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) 118 119 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 120 121 #define CONFIG_SYS_DDRCDR (\ 122 DDRCDR_EN | \ 123 DDRCDR_Q_DRN) 124 #define CONFIG_SYS_DDR_MODE 0x47860452 125 #define CONFIG_SYS_DDR_MODE2 0x8080c000 126 127 #define CONFIG_SYS_DDR_TIMING_0 (\ 128 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 129 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 130 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 131 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 132 (0 << TIMING_CFG0_WWT_SHIFT) | \ 133 (0 << TIMING_CFG0_RRT_SHIFT) | \ 134 (0 << TIMING_CFG0_WRT_SHIFT) | \ 135 (0 << TIMING_CFG0_RWT_SHIFT)) 136 137 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ 138 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 139 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 140 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 141 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 142 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 143 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 144 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 145 146 #define CONFIG_SYS_DDR_TIMING_2 (\ 147 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 148 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 149 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 150 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 151 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 152 (5 << TIMING_CFG2_CPO_SHIFT) | \ 153 (0 << TIMING_CFG2_ADD_LAT_SHIFT)) 154 155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 156 157 /* EEprom support */ 158 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 159 160 /* 161 * Local Bus Configuration & Clock Setup 162 */ 163 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 164 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 165 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 166 167 /* 168 * PAXE on the local bus CS3 169 */ 170 #define CONFIG_SYS_PAXE_BASE 0xA0000000 171 #define CONFIG_SYS_PAXE_SIZE 256 172 173 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE 174 175 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ 176 177 #define CONFIG_SYS_BR3_PRELIM (\ 178 CONFIG_SYS_PAXE_BASE | \ 179 (1 << BR_PS_SHIFT) | \ 180 BR_V) 181 182 #define CONFIG_SYS_OR3_PRELIM (\ 183 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ 184 OR_GPCM_CSNT | \ 185 OR_GPCM_ACS_DIV2 | \ 186 OR_GPCM_SCY_2 | \ 187 OR_GPCM_TRLX | \ 188 OR_GPCM_EAD) 189 190 #ifdef CONFIG_KMCOGE5NE 191 /* 192 * BFTIC3 on the local bus CS4 193 */ 194 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 195 #define CONFIG_SYS_BFTIC3_SIZE 256 196 197 #define CONFIG_SYS_BR4_PRELIM (\ 198 CONFIG_SYS_BFTIC3_BASE |\ 199 (1 << BR_PS_SHIFT) | \ 200 BR_V) 201 202 #define CONFIG_SYS_OR4_PRELIM (\ 203 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\ 204 OR_GPCM_CSNT | \ 205 OR_GPCM_ACS_DIV2 |\ 206 OR_GPCM_SCY_2 |\ 207 OR_GPCM_TRLX |\ 208 OR_GPCM_EAD) 209 #endif 210 211 /* 212 * MMU Setup 213 */ 214 215 /* PAXE: icache cacheable, but dcache-inhibit and guarded */ 216 #define CONFIG_SYS_IBAT5L (\ 217 CONFIG_SYS_PAXE_BASE | \ 218 BATL_PP_10 | \ 219 BATL_MEMCOHERENCE) 220 221 #define CONFIG_SYS_IBAT5U (\ 222 CONFIG_SYS_PAXE_BASE | \ 223 BATU_BL_256M | \ 224 BATU_VS | \ 225 BATU_VP) 226 227 #define CONFIG_SYS_DBAT5L (\ 228 CONFIG_SYS_PAXE_BASE | \ 229 BATL_PP_10 | \ 230 BATL_CACHEINHIBIT | \ 231 BATL_GUARDEDSTORAGE) 232 233 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 234 235 236 #ifdef CONFIG_KMCOGE5NE 237 /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ 238 #define CONFIG_SYS_IBAT6L (\ 239 CONFIG_SYS_BFTIC3_BASE | \ 240 BATL_PP_10 | \ 241 BATL_MEMCOHERENCE) 242 243 #define CONFIG_SYS_IBAT6U (\ 244 CONFIG_SYS_BFTIC3_BASE | \ 245 BATU_BL_256M | \ 246 BATU_VS | \ 247 BATU_VP) 248 249 #define CONFIG_SYS_DBAT6L (\ 250 CONFIG_SYS_BFTIC3_BASE | \ 251 BATL_PP_10 | \ 252 BATL_CACHEINHIBIT | \ 253 BATL_GUARDEDSTORAGE) 254 255 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 256 257 /* DDR/LBC SDRAM next 256M: cacheable */ 258 #define CONFIG_SYS_IBAT7L (\ 259 CONFIG_SYS_SDRAM_BASE2 |\ 260 BATL_PP_10 |\ 261 BATL_CACHEINHIBIT |\ 262 BATL_GUARDEDSTORAGE) 263 264 #define CONFIG_SYS_IBAT7U (\ 265 CONFIG_SYS_SDRAM_BASE2 |\ 266 BATU_BL_256M |\ 267 BATU_VS |\ 268 BATU_VP) 269 /* enable POST tests */ 270 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) 271 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ 272 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END 273 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ 274 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ 275 #define CONFIG_CMD_DIAG /* so that testpin is inquired for POST test */ 276 277 #else 278 #define CONFIG_SYS_IBAT6L (0) 279 #define CONFIG_SYS_IBAT6U (0) 280 #define CONFIG_SYS_IBAT7L (0) 281 #define CONFIG_SYS_IBAT7U (0) 282 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 283 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 284 #endif 285 286 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 287 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 288 289 #endif /* CONFIG */ 290