1 /* 2 * (C) Copyright 2012 3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com> 4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_GENERIC_BOARD 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 /* KMBEC FPGA (PRIO) */ 16 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 17 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 18 19 #if defined CONFIG_KMETER1 20 #define CONFIG_HOSTNAME kmeter1 21 #define CONFIG_KM_BOARD_NAME "kmeter1" 22 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" 23 #elif defined CONFIG_KMCOGE5NE 24 #define CONFIG_HOSTNAME kmcoge5ne 25 #define CONFIG_KM_BOARD_NAME "kmcoge5ne" 26 #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" 27 #define CONFIG_CMD_NAND 28 #define CONFIG_NAND_ECC_BCH 29 #define CONFIG_BCH 30 #define CONFIG_NAND_KMETER1 31 #define CONFIG_SYS_MAX_NAND_DEVICE 1 32 #define NAND_MAX_CHIPS 1 33 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ 34 35 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" 36 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" 37 #define MTDIDS_DEFAULT "nor0=boot,nand0=app" 38 39 #define MTDPARTS_DEFAULT "mtdparts=" \ 40 "boot:" \ 41 "768k(u-boot)," \ 42 "128k(env)," \ 43 "128k(envred)," \ 44 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \ 45 "app:" \ 46 "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");" 47 #else 48 #error ("Board not supported") 49 #endif 50 51 /* 52 * High Level Configuration Options 53 */ 54 #define CONFIG_QE /* Has QE */ 55 #define CONFIG_MPC8360 /* MPC8360 CPU specific */ 56 57 #define CONFIG_SYS_TEXT_BASE 0xF0000000 58 59 /* include common defines/options for all 83xx Keymile boards */ 60 #include "km/km83xx-common.h" 61 62 /* 63 * System IO Setup 64 */ 65 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) 66 67 /* 68 * Hardware Reset Configuration Word 69 */ 70 #define CONFIG_SYS_HRCW_LOW (\ 71 HRCWL_CSB_TO_CLKIN_4X1 | \ 72 HRCWL_CORE_TO_CSB_2X1 | \ 73 HRCWL_CE_PLL_VCO_DIV_2 | \ 74 HRCWL_CE_TO_PLL_1X6) 75 76 #define CONFIG_SYS_HRCW_HIGH (\ 77 HRCWH_CORE_ENABLE | \ 78 HRCWH_FROM_0X00000100 | \ 79 HRCWH_BOOTSEQ_DISABLE | \ 80 HRCWH_SW_WATCHDOG_DISABLE | \ 81 HRCWH_ROM_LOC_LOCAL_16BIT | \ 82 HRCWH_BIG_ENDIAN | \ 83 HRCWH_LALE_EARLY | \ 84 HRCWH_LDP_CLEAR) 85 86 /** 87 * DDR RAM settings 88 */ 89 #define CONFIG_SYS_DDR_SDRAM_CFG (\ 90 SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 91 SDRAM_CFG_SREN | \ 92 SDRAM_CFG_HSE) 93 94 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 95 96 #ifdef CONFIG_KMCOGE5NE 97 /** 98 * KMCOGE5NE has 512 MB RAM 99 */ 100 #define CONFIG_SYS_DDR_CS0_CONFIG (\ 101 CSCONFIG_EN | \ 102 CSCONFIG_AP | \ 103 CSCONFIG_ODT_RD_ONLY_CURRENT | \ 104 CSCONFIG_BANK_BIT_3 | \ 105 CSCONFIG_ROW_BIT_13 | \ 106 CSCONFIG_COL_BIT_10) 107 #else 108 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 109 CSCONFIG_ROW_BIT_13 | \ 110 CSCONFIG_COL_BIT_10 | \ 111 CSCONFIG_ODT_RD_ONLY_CURRENT) 112 #endif 113 114 #define CONFIG_SYS_DDR_CLK_CNTL (\ 115 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 116 117 #define CONFIG_SYS_DDR_INTERVAL (\ 118 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 119 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) 120 121 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 122 123 #define CONFIG_SYS_DDRCDR (\ 124 DDRCDR_EN | \ 125 DDRCDR_Q_DRN) 126 #define CONFIG_SYS_DDR_MODE 0x47860452 127 #define CONFIG_SYS_DDR_MODE2 0x8080c000 128 129 #define CONFIG_SYS_DDR_TIMING_0 (\ 130 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 131 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 132 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 133 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 134 (0 << TIMING_CFG0_WWT_SHIFT) | \ 135 (0 << TIMING_CFG0_RRT_SHIFT) | \ 136 (0 << TIMING_CFG0_WRT_SHIFT) | \ 137 (0 << TIMING_CFG0_RWT_SHIFT)) 138 139 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ 140 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 141 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 142 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 143 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 144 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 145 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 146 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 147 148 #define CONFIG_SYS_DDR_TIMING_2 (\ 149 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 150 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 151 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 152 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 153 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 154 (5 << TIMING_CFG2_CPO_SHIFT) | \ 155 (0 << TIMING_CFG2_ADD_LAT_SHIFT)) 156 157 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 158 159 /* EEprom support */ 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 161 162 /* 163 * Local Bus Configuration & Clock Setup 164 */ 165 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 166 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 167 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 168 169 /* 170 * PAXE on the local bus CS3 171 */ 172 #define CONFIG_SYS_PAXE_BASE 0xA0000000 173 #define CONFIG_SYS_PAXE_SIZE 256 174 175 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE 176 177 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ 178 179 #define CONFIG_SYS_BR3_PRELIM (\ 180 CONFIG_SYS_PAXE_BASE | \ 181 (1 << BR_PS_SHIFT) | \ 182 BR_V) 183 184 #define CONFIG_SYS_OR3_PRELIM (\ 185 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ 186 OR_GPCM_CSNT | \ 187 OR_GPCM_ACS_DIV2 | \ 188 OR_GPCM_SCY_2 | \ 189 OR_GPCM_TRLX | \ 190 OR_GPCM_EAD) 191 192 #ifdef CONFIG_KMCOGE5NE 193 /* 194 * BFTIC3 on the local bus CS4 195 */ 196 #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 197 #define CONFIG_SYS_BFTIC3_SIZE 256 198 199 #define CONFIG_SYS_BR4_PRELIM (\ 200 CONFIG_SYS_BFTIC3_BASE |\ 201 (1 << BR_PS_SHIFT) | \ 202 BR_V) 203 204 #define CONFIG_SYS_OR4_PRELIM (\ 205 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\ 206 OR_GPCM_CSNT | \ 207 OR_GPCM_ACS_DIV2 |\ 208 OR_GPCM_SCY_2 |\ 209 OR_GPCM_TRLX |\ 210 OR_GPCM_EAD) 211 #endif 212 213 /* 214 * MMU Setup 215 */ 216 217 /* PAXE: icache cacheable, but dcache-inhibit and guarded */ 218 #define CONFIG_SYS_IBAT5L (\ 219 CONFIG_SYS_PAXE_BASE | \ 220 BATL_PP_10 | \ 221 BATL_MEMCOHERENCE) 222 223 #define CONFIG_SYS_IBAT5U (\ 224 CONFIG_SYS_PAXE_BASE | \ 225 BATU_BL_256M | \ 226 BATU_VS | \ 227 BATU_VP) 228 229 #define CONFIG_SYS_DBAT5L (\ 230 CONFIG_SYS_PAXE_BASE | \ 231 BATL_PP_10 | \ 232 BATL_CACHEINHIBIT | \ 233 BATL_GUARDEDSTORAGE) 234 235 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 236 237 238 #ifdef CONFIG_KMCOGE5NE 239 /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ 240 #define CONFIG_SYS_IBAT6L (\ 241 CONFIG_SYS_BFTIC3_BASE | \ 242 BATL_PP_10 | \ 243 BATL_MEMCOHERENCE) 244 245 #define CONFIG_SYS_IBAT6U (\ 246 CONFIG_SYS_BFTIC3_BASE | \ 247 BATU_BL_256M | \ 248 BATU_VS | \ 249 BATU_VP) 250 251 #define CONFIG_SYS_DBAT6L (\ 252 CONFIG_SYS_BFTIC3_BASE | \ 253 BATL_PP_10 | \ 254 BATL_CACHEINHIBIT | \ 255 BATL_GUARDEDSTORAGE) 256 257 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 258 259 /* DDR/LBC SDRAM next 256M: cacheable */ 260 #define CONFIG_SYS_IBAT7L (\ 261 CONFIG_SYS_SDRAM_BASE2 |\ 262 BATL_PP_10 |\ 263 BATL_CACHEINHIBIT |\ 264 BATL_GUARDEDSTORAGE) 265 266 #define CONFIG_SYS_IBAT7U (\ 267 CONFIG_SYS_SDRAM_BASE2 |\ 268 BATU_BL_256M |\ 269 BATU_VS |\ 270 BATU_VP) 271 /* enable POST tests */ 272 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) 273 #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ 274 #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END 275 #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ 276 #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ 277 #define CONFIG_CMD_DIAG /* so that testpin is inquired for POST test */ 278 279 #else 280 #define CONFIG_SYS_IBAT6L (0) 281 #define CONFIG_SYS_IBAT6U (0) 282 #define CONFIG_SYS_IBAT7L (0) 283 #define CONFIG_SYS_IBAT7U (0) 284 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 285 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 286 #endif 287 288 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 289 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 290 291 #endif /* CONFIG */ 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