1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_PHYS_64BIT 12 #define CONFIG_PPC_P2041 13 14 #define CONFIG_SYS_TEXT_BASE 0xfff40000 15 16 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 17 18 /* an additionnal option is required for UBI as subpage access is 19 * supported in u-boot */ 20 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 21 22 #define CONFIG_NAND_ECC_BCH 23 24 #define CONFIG_DISPLAY_BOARDINFO 25 26 /* common KM defines */ 27 #include "keymile-common.h" 28 29 #define CONFIG_SYS_RAMBOOT 30 #define CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 35 36 /* High Level Configuration Options */ 37 #define CONFIG_BOOKE 38 #define CONFIG_E500 /* BOOKE e500 family */ 39 #define CONFIG_E500MC /* BOOKE e500mc family */ 40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 41 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 42 #define CONFIG_MP /* support multiple processors */ 43 44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 45 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 46 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 47 #define CONFIG_PCI /* Enable PCI/PCIE */ 48 #define CONFIG_PCIE1 /* PCIE controller 1 */ 49 #define CONFIG_PCIE3 /* PCIE controller 3 */ 50 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 51 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 52 53 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 54 55 #define CONFIG_FSL_LAW /* Use common FSL init code */ 56 57 /* Environment in SPI Flash */ 58 #define CONFIG_SYS_EXTRA_ENV_RELOC 59 #define CONFIG_ENV_IS_IN_SPI_FLASH 60 #define CONFIG_ENV_SPI_BUS 0 61 #define CONFIG_ENV_SPI_CS 0 62 #define CONFIG_ENV_SPI_MAX_HZ 20000000 63 #define CONFIG_ENV_SPI_MODE 0 64 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 65 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 66 #define CONFIG_ENV_SECT_SIZE 0x010000 67 #define CONFIG_ENV_OFFSET_REDUND 0x110000 68 #define CONFIG_ENV_TOTAL_SIZE 0x020000 69 70 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 71 72 #ifndef __ASSEMBLY__ 73 unsigned long get_board_sys_clk(unsigned long dummy); 74 #endif 75 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 76 77 /* 78 * These can be toggled for performance analysis, otherwise use default. 79 */ 80 #define CONFIG_SYS_CACHE_STASHING 81 #define CONFIG_BACKSIDE_L2_CACHE 82 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 83 #define CONFIG_BTB /* toggle branch predition */ 84 85 #define CONFIG_ENABLE_36BIT_PHYS 86 87 #define CONFIG_ADDR_MAP 88 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 89 90 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 91 92 /* 93 * Config the L3 Cache as L3 SRAM 94 */ 95 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 96 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 97 CONFIG_RAMBOOT_TEXT_BASE) 98 #define CONFIG_SYS_L3_SIZE (1024 << 10) 99 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 100 101 #define CONFIG_SYS_DCSRBAR 0xf0000000 102 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 103 104 /* 105 * DDR Setup 106 */ 107 #define CONFIG_VERY_BIG_RAM 108 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 110 111 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 112 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 113 114 #define CONFIG_DDR_SPD 115 #define CONFIG_SYS_FSL_DDR3 116 #define CONFIG_FSL_DDR_INTERACTIVE 117 118 #define CONFIG_SYS_SPD_BUS_NUM 0 119 #define SPD_EEPROM_ADDRESS 0x54 120 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 121 122 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 123 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 124 125 /****************************************************************************** 126 * (PRAM usage) 127 * ... ------------------------------------------------------- 128 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 129 * ... |<------------------- pram -------------------------->| 130 * ... ------------------------------------------------------- 131 * @END_OF_RAM: 132 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 133 * @CONFIG_KM_PHRAM: address for /var 134 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 135 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 136 */ 137 138 /* size of rootfs in RAM */ 139 #define CONFIG_KM_ROOTFSSIZE 0x0 140 /* pseudo-non volatile RAM [hex] */ 141 #define CONFIG_KM_PNVRAM 0x80000 142 /* physical RAM MTD size [hex] */ 143 #define CONFIG_KM_PHRAM 0x100000 144 /* reserved pram area at the end of memory [hex] 145 * u-boot reserves some memory for the MP boot page */ 146 #define CONFIG_KM_RESERVED_PRAM 0x1000 147 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 148 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 149 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 150 151 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 152 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 153 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 154 155 /* 156 * Local Bus Definitions 157 */ 158 159 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 160 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 161 162 /* Nand Flash */ 163 #define CONFIG_NAND_FSL_ELBC 164 #define CONFIG_SYS_NAND_BASE 0xffa00000 165 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 166 167 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 168 #define CONFIG_SYS_MAX_NAND_DEVICE 1 169 #define CONFIG_CMD_NAND 170 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 171 172 #define CONFIG_BCH 173 174 /* NAND flash config */ 175 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 176 | BR_PS_8 /* Port Size = 8 bit */ \ 177 | BR_MS_FCM /* MSEL = FCM */ \ 178 | BR_V) /* valid */ 179 180 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 181 | OR_FCM_BCTLD /* LBCTL not ass */ \ 182 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 183 | OR_FCM_RST /* 1 clk read setup */ \ 184 | OR_FCM_PGS /* Large page size */ \ 185 | OR_FCM_CST) /* 0.25 command setup */ 186 187 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 188 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 189 190 /* QRIO FPGA */ 191 #define CONFIG_SYS_QRIO_BASE 0xfb000000 192 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 193 194 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 195 | BR_PS_8 /* Port Size 8 bits */ \ 196 | BR_DECC_OFF /* no error corr */ \ 197 | BR_MS_GPCM /* MSEL = GPCM */ \ 198 | BR_V) /* valid */ 199 200 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 201 | OR_GPCM_BCTLD /* no LCTL assert */ \ 202 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 203 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 204 | OR_GPCM_TRLX /* relaxed tmgs */ \ 205 | OR_GPCM_EAD) /* extra bus clk cycles */ 206 207 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 208 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 209 210 /* bootcounter in QRIO */ 211 #define CONFIG_BOOTCOUNT_LIMIT 212 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 213 214 #define CONFIG_BOARD_EARLY_INIT_F 215 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 216 #define CONFIG_MISC_INIT_F 217 #define CONFIG_MISC_INIT_R 218 #define CONFIG_LAST_STAGE_INIT 219 220 #define CONFIG_HWCONFIG 221 222 /* define to use L1 as initial stack */ 223 #define CONFIG_L1_INIT_RAM 224 #define CONFIG_SYS_INIT_RAM_LOCK 225 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 228 /* The assembler doesn't like typecast */ 229 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 230 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 231 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 232 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 233 234 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 235 GENERATED_GBL_DATA_SIZE) 236 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 237 238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 239 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 240 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 241 242 /* Serial Port - controlled on board with jumper J8 243 * open - index 2 244 * shorted - index 1 245 */ 246 #define CONFIG_CONS_INDEX 1 247 #define CONFIG_SYS_NS16550_SERIAL 248 #define CONFIG_SYS_NS16550_REG_SIZE 1 249 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 250 251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 253 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 254 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 255 256 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 257 258 /* I2C */ 259 260 #define CONFIG_SYS_I2C 261 #define CONFIG_SYS_I2C_INIT_BOARD 262 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 263 #define CONFIG_SYS_NUM_I2C_BUSES 3 264 #define CONFIG_SYS_I2C_MAX_HOPS 1 265 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 266 #define CONFIG_I2C_MULTI_BUS 267 #define CONFIG_I2C_CMD_TREE 268 #define CONFIG_SYS_FSL_I2C_SPEED 400000 269 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 270 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 271 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 272 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 273 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 274 } 275 #ifndef __ASSEMBLY__ 276 void set_sda(int state); 277 void set_scl(int state); 278 int get_sda(void); 279 int get_scl(void); 280 #endif 281 282 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 283 284 /* 285 * eSPI - Enhanced SPI 286 */ 287 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 288 #define CONFIG_SF_DEFAULT_SPEED 20000000 289 #define CONFIG_SF_DEFAULT_MODE 0 290 291 /* 292 * General PCI 293 * Memory space is mapped 1-1, but I/O space must start from 0. 294 */ 295 296 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 297 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 298 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 299 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 300 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 301 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 302 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 303 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 304 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 305 306 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 307 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 308 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 309 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 310 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 311 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 312 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 313 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 314 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 315 316 /* Qman/Bman */ 317 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 318 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 319 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 320 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 321 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 322 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 323 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 324 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 325 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 326 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 327 CONFIG_SYS_BMAN_CENA_SIZE) 328 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 329 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 330 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 331 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 332 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 333 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 334 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 335 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 336 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 337 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 338 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 339 CONFIG_SYS_QMAN_CENA_SIZE) 340 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 341 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 342 343 #define CONFIG_SYS_DPAA_FMAN 344 #define CONFIG_SYS_DPAA_PME 345 /* Default address of microcode for the Linux Fman driver 346 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 347 * ucode is stored after env, so we got 0x120000. 348 */ 349 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 350 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 351 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 352 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 353 354 #define CONFIG_FMAN_ENET 355 #define CONFIG_PHYLIB_10G 356 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 357 358 #define CONFIG_PCI_INDIRECT_BRIDGE 359 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 360 361 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 362 #define CONFIG_DOS_PARTITION 363 364 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 365 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 366 #define CONFIG_SYS_TBIPA_VALUE 8 367 #define CONFIG_PHYLIB /* recommended PHY management */ 368 #define CONFIG_ETHPRIME "FM1@DTSEC5" 369 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 370 371 /* 372 * Environment 373 */ 374 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 375 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 376 377 /* 378 * Hardware Watchdog 379 */ 380 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 381 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 382 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 383 384 385 /* 386 * additionnal command line configuration. 387 */ 388 #define CONFIG_CMD_PCI 389 #define CONFIG_CMD_ERRATA 390 391 /* we don't need flash support */ 392 #define CONFIG_SYS_NO_FLASH 393 #undef CONFIG_FLASH_CFI_MTD 394 #undef CONFIG_JFFS2_CMDLINE 395 396 /* 397 * For booting Linux, the board info and command line data 398 * have to be in the first 64 MB of memory, since this is 399 * the maximum mapped by the Linux kernel during initialization. 400 */ 401 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 402 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 403 404 #ifdef CONFIG_CMD_KGDB 405 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 406 #endif 407 408 #define __USB_PHY_TYPE utmi 409 410 /* 411 * Environment Configuration 412 */ 413 #define CONFIG_ENV_OVERWRITE 414 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 415 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 416 #endif 417 418 #ifndef MTDIDS_DEFAULT 419 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 420 #endif /* MTDIDS_DEFAULT */ 421 422 #ifndef MTDPARTS_DEFAULT 423 # define MTDPARTS_DEFAULT "mtdparts=" \ 424 "fsl_elbc_nand:" \ 425 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 426 #endif /* MTDPARTS_DEFAULT */ 427 428 /* architecture specific default bootargs */ 429 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 430 431 /* FIXME: FDT_ADDR is unspecified */ 432 #define CONFIG_KM_DEF_ENV_CPU \ 433 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 434 "cramfsloadfdt=" \ 435 "cramfsload ${fdt_addr_r} " \ 436 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 437 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 438 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 439 "update=" \ 440 "sf probe 0;sf erase 0 +${filesize};" \ 441 "sf write ${load_addr_r} 0 ${filesize};\0" \ 442 "set_fdthigh=true\0" \ 443 "checkfdt=true\0" \ 444 "" 445 446 #define CONFIG_HW_ENV_SETTINGS \ 447 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 448 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 449 "usb_dr_mode=host\0" 450 451 #define CONFIG_KM_NEW_ENV \ 452 "newenv=sf probe 0;" \ 453 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 454 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 455 456 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 457 #ifndef CONFIG_KM_DEF_ARCH 458 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 459 #endif 460 461 #define CONFIG_EXTRA_ENV_SETTINGS \ 462 CONFIG_KM_DEF_ENV \ 463 CONFIG_KM_DEF_ARCH \ 464 CONFIG_KM_NEW_ENV \ 465 CONFIG_HW_ENV_SETTINGS \ 466 "EEprom_ivm=pca9547:70:9\0" \ 467 "" 468 469 #endif /* _CONFIG_KMP204X_H */ 470