1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_PHYS_64BIT 12 #define CONFIG_PPC_P2041 13 14 #define CONFIG_SYS_TEXT_BASE 0xfff40000 15 16 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 17 18 /* an additionnal option is required for UBI as subpage access is 19 * supported in u-boot */ 20 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 21 22 #define CONFIG_NAND_ECC_BCH 23 24 #define CONFIG_SYS_GENERIC_BOARD 25 #define CONFIG_DISPLAY_BOARDINFO 26 27 /* common KM defines */ 28 #include "keymile-common.h" 29 30 #define CONFIG_SYS_RAMBOOT 31 #define CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 36 37 /* High Level Configuration Options */ 38 #define CONFIG_BOOKE 39 #define CONFIG_E500 /* BOOKE e500 family */ 40 #define CONFIG_E500MC /* BOOKE e500mc family */ 41 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 43 #define CONFIG_MP /* support multiple processors */ 44 45 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 46 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 47 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 48 #define CONFIG_PCI /* Enable PCI/PCIE */ 49 #define CONFIG_PCIE1 /* PCIE controler 1 */ 50 #define CONFIG_PCIE3 /* PCIE controler 3 */ 51 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 52 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 53 54 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 55 56 #define CONFIG_FSL_LAW /* Use common FSL init code */ 57 58 /* Environment in SPI Flash */ 59 #define CONFIG_SYS_EXTRA_ENV_RELOC 60 #define CONFIG_ENV_IS_IN_SPI_FLASH 61 #define CONFIG_ENV_SPI_BUS 0 62 #define CONFIG_ENV_SPI_CS 0 63 #define CONFIG_ENV_SPI_MAX_HZ 20000000 64 #define CONFIG_ENV_SPI_MODE 0 65 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 66 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 67 #define CONFIG_ENV_SECT_SIZE 0x010000 68 #define CONFIG_ENV_OFFSET_REDUND 0x110000 69 #define CONFIG_ENV_TOTAL_SIZE 0x020000 70 71 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 72 73 #ifndef __ASSEMBLY__ 74 unsigned long get_board_sys_clk(unsigned long dummy); 75 #endif 76 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 77 78 /* 79 * These can be toggled for performance analysis, otherwise use default. 80 */ 81 #define CONFIG_SYS_CACHE_STASHING 82 #define CONFIG_BACKSIDE_L2_CACHE 83 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 84 #define CONFIG_BTB /* toggle branch predition */ 85 86 #define CONFIG_ENABLE_36BIT_PHYS 87 88 #define CONFIG_ADDR_MAP 89 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 90 91 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 92 93 /* 94 * Config the L3 Cache as L3 SRAM 95 */ 96 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 97 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 98 CONFIG_RAMBOOT_TEXT_BASE) 99 #define CONFIG_SYS_L3_SIZE (1024 << 10) 100 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 101 102 #define CONFIG_SYS_DCSRBAR 0xf0000000 103 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 104 105 /* 106 * DDR Setup 107 */ 108 #define CONFIG_VERY_BIG_RAM 109 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 110 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 111 112 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 113 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 114 115 #define CONFIG_DDR_SPD 116 #define CONFIG_SYS_FSL_DDR3 117 #define CONFIG_FSL_DDR_INTERACTIVE 118 119 #define CONFIG_SYS_SPD_BUS_NUM 0 120 #define SPD_EEPROM_ADDRESS 0x54 121 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 122 123 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 125 126 /****************************************************************************** 127 * (PRAM usage) 128 * ... ------------------------------------------------------- 129 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 130 * ... |<------------------- pram -------------------------->| 131 * ... ------------------------------------------------------- 132 * @END_OF_RAM: 133 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 134 * @CONFIG_KM_PHRAM: address for /var 135 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 136 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 137 */ 138 139 /* size of rootfs in RAM */ 140 #define CONFIG_KM_ROOTFSSIZE 0x0 141 /* pseudo-non volatile RAM [hex] */ 142 #define CONFIG_KM_PNVRAM 0x80000 143 /* physical RAM MTD size [hex] */ 144 #define CONFIG_KM_PHRAM 0x100000 145 /* reserved pram area at the end of memory [hex] 146 * u-boot reserves some memory for the MP boot page */ 147 #define CONFIG_KM_RESERVED_PRAM 0x1000 148 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 149 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 150 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 151 152 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 153 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 154 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 155 156 /* 157 * Local Bus Definitions 158 */ 159 160 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 161 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 162 163 /* Nand Flash */ 164 #define CONFIG_NAND_FSL_ELBC 165 #define CONFIG_SYS_NAND_BASE 0xffa00000 166 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 167 168 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 169 #define CONFIG_SYS_MAX_NAND_DEVICE 1 170 #define CONFIG_CMD_NAND 171 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 172 173 #define CONFIG_BCH 174 175 /* NAND flash config */ 176 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 177 | BR_PS_8 /* Port Size = 8 bit */ \ 178 | BR_MS_FCM /* MSEL = FCM */ \ 179 | BR_V) /* valid */ 180 181 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 182 | OR_FCM_BCTLD /* LBCTL not ass */ \ 183 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 184 | OR_FCM_RST /* 1 clk read setup */ \ 185 | OR_FCM_PGS /* Large page size */ \ 186 | OR_FCM_CST) /* 0.25 command setup */ 187 188 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 189 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 190 191 /* QRIO FPGA */ 192 #define CONFIG_SYS_QRIO_BASE 0xfb000000 193 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 194 195 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 196 | BR_PS_8 /* Port Size 8 bits */ \ 197 | BR_DECC_OFF /* no error corr */ \ 198 | BR_MS_GPCM /* MSEL = GPCM */ \ 199 | BR_V) /* valid */ 200 201 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 202 | OR_GPCM_BCTLD /* no LCTL assert */ \ 203 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 204 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 205 | OR_GPCM_TRLX /* relaxed tmgs */ \ 206 | OR_GPCM_EAD) /* extra bus clk cycles */ 207 208 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 209 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 210 211 /* bootcounter in QRIO */ 212 #define CONFIG_BOOTCOUNT_LIMIT 213 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 214 215 #define CONFIG_BOARD_EARLY_INIT_F 216 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 217 #define CONFIG_MISC_INIT_F 218 #define CONFIG_MISC_INIT_R 219 #define CONFIG_LAST_STAGE_INIT 220 221 #define CONFIG_HWCONFIG 222 223 /* define to use L1 as initial stack */ 224 #define CONFIG_L1_INIT_RAM 225 #define CONFIG_SYS_INIT_RAM_LOCK 226 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 229 /* The assembler doesn't like typecast */ 230 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 231 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 232 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 233 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 234 235 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 236 GENERATED_GBL_DATA_SIZE) 237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 238 239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 240 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 241 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 242 243 /* Serial Port - controlled on board with jumper J8 244 * open - index 2 245 * shorted - index 1 246 */ 247 #define CONFIG_CONS_INDEX 1 248 #define CONFIG_SYS_NS16550 249 #define CONFIG_SYS_NS16550_SERIAL 250 #define CONFIG_SYS_NS16550_REG_SIZE 1 251 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 252 253 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 254 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 255 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 256 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 257 258 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 259 260 /* Use the HUSH parser */ 261 #define CONFIG_SYS_HUSH_PARSER 262 263 /* pass open firmware flat tree */ 264 #define CONFIG_OF_LIBFDT 265 #define CONFIG_OF_BOARD_SETUP 266 #define CONFIG_OF_STDOUT_VIA_ALIAS 267 268 /* new uImage format support */ 269 #define CONFIG_FIT 270 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 271 272 /* I2C */ 273 274 #define CONFIG_SYS_I2C 275 #define CONFIG_SYS_I2C_INIT_BOARD 276 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 277 #define CONFIG_SYS_NUM_I2C_BUSES 3 278 #define CONFIG_SYS_I2C_MAX_HOPS 1 279 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 280 #define CONFIG_I2C_MULTI_BUS 281 #define CONFIG_I2C_CMD_TREE 282 #define CONFIG_SYS_FSL_I2C_SPEED 400000 283 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 284 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 285 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 286 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 287 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 288 } 289 #ifndef __ASSEMBLY__ 290 void set_sda(int state); 291 void set_scl(int state); 292 int get_sda(void); 293 int get_scl(void); 294 #endif 295 296 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 297 298 /* 299 * eSPI - Enhanced SPI 300 */ 301 #define CONFIG_FSL_ESPI 302 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 303 #define CONFIG_SPI_FLASH_STMICRO 304 #define CONFIG_SPI_FLASH_SPANSION 305 #define CONFIG_CMD_SF 306 #define CONFIG_SF_DEFAULT_SPEED 20000000 307 #define CONFIG_SF_DEFAULT_MODE 0 308 309 /* 310 * General PCI 311 * Memory space is mapped 1-1, but I/O space must start from 0. 312 */ 313 314 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 315 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 316 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 317 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 318 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 319 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 320 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 321 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 322 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 323 324 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 325 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 326 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 327 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 328 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 329 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 330 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 331 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 332 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 333 334 /* Qman/Bman */ 335 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 336 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 337 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 338 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 339 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 340 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 341 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 342 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 343 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 344 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 345 CONFIG_SYS_BMAN_CENA_SIZE) 346 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 347 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 348 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 349 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 350 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 351 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 352 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 353 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 354 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 355 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 356 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 357 CONFIG_SYS_QMAN_CENA_SIZE) 358 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 359 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 360 361 #define CONFIG_SYS_DPAA_FMAN 362 #define CONFIG_SYS_DPAA_PME 363 /* Default address of microcode for the Linux Fman driver 364 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 365 * ucode is stored after env, so we got 0x120000. 366 */ 367 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 368 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 369 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 370 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 371 372 #define CONFIG_FMAN_ENET 373 #define CONFIG_PHYLIB_10G 374 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 375 376 #define CONFIG_PCI_INDIRECT_BRIDGE 377 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 378 #define CONFIG_E1000 379 380 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 381 #define CONFIG_DOS_PARTITION 382 383 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 384 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 385 #define CONFIG_SYS_TBIPA_VALUE 8 386 #define CONFIG_PHYLIB /* recommended PHY management */ 387 #define CONFIG_ETHPRIME "FM1@DTSEC5" 388 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 389 390 /* 391 * Environment 392 */ 393 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 394 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 395 396 /* 397 * Hardware Watchdog 398 */ 399 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 400 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 401 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 402 403 404 /* 405 * additionnal command line configuration. 406 */ 407 #define CONFIG_CMD_PCI 408 #define CONFIG_CMD_ERRATA 409 410 /* we don't need flash support */ 411 #define CONFIG_SYS_NO_FLASH 412 #undef CONFIG_FLASH_CFI_MTD 413 #undef CONFIG_JFFS2_CMDLINE 414 415 /* 416 * For booting Linux, the board info and command line data 417 * have to be in the first 64 MB of memory, since this is 418 * the maximum mapped by the Linux kernel during initialization. 419 */ 420 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 421 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 422 423 #ifdef CONFIG_CMD_KGDB 424 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 425 #endif 426 427 #define __USB_PHY_TYPE utmi 428 429 /* 430 * Environment Configuration 431 */ 432 #define CONFIG_ENV_OVERWRITE 433 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 434 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 435 #endif 436 437 #ifndef MTDIDS_DEFAULT 438 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 439 #endif /* MTDIDS_DEFAULT */ 440 441 #ifndef MTDPARTS_DEFAULT 442 # define MTDPARTS_DEFAULT "mtdparts=" \ 443 "fsl_elbc_nand:" \ 444 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 445 #endif /* MTDPARTS_DEFAULT */ 446 447 /* architecture specific default bootargs */ 448 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 449 450 /* FIXME: FDT_ADDR is unspecified */ 451 #define CONFIG_KM_DEF_ENV_CPU \ 452 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 453 "cramfsloadfdt=" \ 454 "cramfsload ${fdt_addr_r} " \ 455 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 456 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 457 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 458 "update=" \ 459 "sf probe 0;sf erase 0 +${filesize};" \ 460 "sf write ${load_addr_r} 0 ${filesize};\0" \ 461 "set_fdthigh=true\0" \ 462 "" 463 464 #define CONFIG_HW_ENV_SETTINGS \ 465 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 466 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 467 "usb_dr_mode=host\0" 468 469 #define CONFIG_KM_NEW_ENV \ 470 "newenv=sf probe 0;" \ 471 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 472 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 473 474 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 475 #ifndef CONFIG_KM_DEF_ARCH 476 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 477 #endif 478 479 #define CONFIG_EXTRA_ENV_SETTINGS \ 480 CONFIG_KM_DEF_ENV \ 481 CONFIG_KM_DEF_ARCH \ 482 CONFIG_KM_NEW_ENV \ 483 CONFIG_HW_ENV_SETTINGS \ 484 "EEprom_ivm=pca9547:70:9\0" \ 485 "" 486 487 #endif /* _CONFIG_KMP204X_H */ 488