1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_SYS_TEXT_BASE 0xfff40000 12 13 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 14 15 /* an additionnal option is required for UBI as subpage access is 16 * supported in u-boot */ 17 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 18 19 #define CONFIG_NAND_ECC_BCH 20 21 /* common KM defines */ 22 #include "keymile-common.h" 23 24 #define CONFIG_SYS_RAMBOOT 25 #define CONFIG_RAMBOOT_PBL 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 29 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 30 31 /* High Level Configuration Options */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 34 #define CONFIG_MP /* support multiple processors */ 35 36 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 37 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 38 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 39 #define CONFIG_PCIE1 /* PCIE controller 1 */ 40 #define CONFIG_PCIE3 /* PCIE controller 3 */ 41 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 42 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 43 44 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 45 46 /* Environment in SPI Flash */ 47 #define CONFIG_SYS_EXTRA_ENV_RELOC 48 #define CONFIG_ENV_IS_IN_SPI_FLASH 49 #define CONFIG_ENV_SPI_BUS 0 50 #define CONFIG_ENV_SPI_CS 0 51 #define CONFIG_ENV_SPI_MAX_HZ 20000000 52 #define CONFIG_ENV_SPI_MODE 0 53 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 54 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 55 #define CONFIG_ENV_SECT_SIZE 0x010000 56 #define CONFIG_ENV_OFFSET_REDUND 0x110000 57 #define CONFIG_ENV_TOTAL_SIZE 0x020000 58 59 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 60 61 #ifndef __ASSEMBLY__ 62 unsigned long get_board_sys_clk(unsigned long dummy); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_SYS_CACHE_STASHING 70 #define CONFIG_BACKSIDE_L2_CACHE 71 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 72 #define CONFIG_BTB /* toggle branch predition */ 73 74 #define CONFIG_ENABLE_36BIT_PHYS 75 76 #define CONFIG_ADDR_MAP 77 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 78 79 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 80 81 /* 82 * Config the L3 Cache as L3 SRAM 83 */ 84 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 85 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 86 CONFIG_RAMBOOT_TEXT_BASE) 87 #define CONFIG_SYS_L3_SIZE (1024 << 10) 88 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 89 90 #define CONFIG_SYS_DCSRBAR 0xf0000000 91 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 92 93 /* 94 * DDR Setup 95 */ 96 #define CONFIG_VERY_BIG_RAM 97 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 99 100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 101 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 102 103 #define CONFIG_DDR_SPD 104 #define CONFIG_FSL_DDR_INTERACTIVE 105 106 #define CONFIG_SYS_SPD_BUS_NUM 0 107 #define SPD_EEPROM_ADDRESS 0x54 108 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 109 110 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 112 113 /****************************************************************************** 114 * (PRAM usage) 115 * ... ------------------------------------------------------- 116 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 117 * ... |<------------------- pram -------------------------->| 118 * ... ------------------------------------------------------- 119 * @END_OF_RAM: 120 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 121 * @CONFIG_KM_PHRAM: address for /var 122 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 123 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 124 */ 125 126 /* size of rootfs in RAM */ 127 #define CONFIG_KM_ROOTFSSIZE 0x0 128 /* pseudo-non volatile RAM [hex] */ 129 #define CONFIG_KM_PNVRAM 0x80000 130 /* physical RAM MTD size [hex] */ 131 #define CONFIG_KM_PHRAM 0x100000 132 /* reserved pram area at the end of memory [hex] 133 * u-boot reserves some memory for the MP boot page */ 134 #define CONFIG_KM_RESERVED_PRAM 0x1000 135 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 136 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 137 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 138 139 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 140 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 141 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 142 143 /* 144 * Local Bus Definitions 145 */ 146 147 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 148 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 149 150 /* Nand Flash */ 151 #define CONFIG_NAND_FSL_ELBC 152 #define CONFIG_SYS_NAND_BASE 0xffa00000 153 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 154 155 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 156 #define CONFIG_SYS_MAX_NAND_DEVICE 1 157 #define CONFIG_CMD_NAND 158 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 159 160 #define CONFIG_BCH 161 162 /* NAND flash config */ 163 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 164 | BR_PS_8 /* Port Size = 8 bit */ \ 165 | BR_MS_FCM /* MSEL = FCM */ \ 166 | BR_V) /* valid */ 167 168 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 169 | OR_FCM_BCTLD /* LBCTL not ass */ \ 170 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 171 | OR_FCM_RST /* 1 clk read setup */ \ 172 | OR_FCM_PGS /* Large page size */ \ 173 | OR_FCM_CST) /* 0.25 command setup */ 174 175 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 176 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 177 178 /* QRIO FPGA */ 179 #define CONFIG_SYS_QRIO_BASE 0xfb000000 180 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 181 182 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 183 | BR_PS_8 /* Port Size 8 bits */ \ 184 | BR_DECC_OFF /* no error corr */ \ 185 | BR_MS_GPCM /* MSEL = GPCM */ \ 186 | BR_V) /* valid */ 187 188 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 189 | OR_GPCM_BCTLD /* no LCTL assert */ \ 190 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 191 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 192 | OR_GPCM_TRLX /* relaxed tmgs */ \ 193 | OR_GPCM_EAD) /* extra bus clk cycles */ 194 195 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 196 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 197 198 /* bootcounter in QRIO */ 199 #define CONFIG_BOOTCOUNT_LIMIT 200 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 201 202 #define CONFIG_BOARD_EARLY_INIT_F 203 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 204 #define CONFIG_MISC_INIT_F 205 #define CONFIG_MISC_INIT_R 206 #define CONFIG_LAST_STAGE_INIT 207 208 #define CONFIG_HWCONFIG 209 210 /* define to use L1 as initial stack */ 211 #define CONFIG_L1_INIT_RAM 212 #define CONFIG_SYS_INIT_RAM_LOCK 213 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 214 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 215 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 216 /* The assembler doesn't like typecast */ 217 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 218 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 219 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 220 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 221 222 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 223 GENERATED_GBL_DATA_SIZE) 224 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 225 226 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 227 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 228 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 229 230 /* Serial Port - controlled on board with jumper J8 231 * open - index 2 232 * shorted - index 1 233 */ 234 #define CONFIG_CONS_INDEX 1 235 #define CONFIG_SYS_NS16550_SERIAL 236 #define CONFIG_SYS_NS16550_REG_SIZE 1 237 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 238 239 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 240 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 241 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 242 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 243 244 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 245 246 /* I2C */ 247 248 #define CONFIG_SYS_I2C 249 #define CONFIG_SYS_I2C_INIT_BOARD 250 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 251 #define CONFIG_SYS_NUM_I2C_BUSES 3 252 #define CONFIG_SYS_I2C_MAX_HOPS 1 253 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 254 #define CONFIG_I2C_MULTI_BUS 255 #define CONFIG_I2C_CMD_TREE 256 #define CONFIG_SYS_FSL_I2C_SPEED 400000 257 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 258 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 259 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 260 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 261 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 262 } 263 #ifndef __ASSEMBLY__ 264 void set_sda(int state); 265 void set_scl(int state); 266 int get_sda(void); 267 int get_scl(void); 268 #endif 269 270 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 271 272 /* 273 * eSPI - Enhanced SPI 274 */ 275 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 276 #define CONFIG_SF_DEFAULT_SPEED 20000000 277 #define CONFIG_SF_DEFAULT_MODE 0 278 279 /* 280 * General PCI 281 * Memory space is mapped 1-1, but I/O space must start from 0. 282 */ 283 284 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 285 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 286 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 287 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 288 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 289 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 290 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 291 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 292 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 293 294 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 295 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 296 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 297 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 298 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 299 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 300 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 301 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 302 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 303 304 /* Qman/Bman */ 305 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 306 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 307 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 308 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 309 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 310 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 311 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 312 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 313 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 314 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 315 CONFIG_SYS_BMAN_CENA_SIZE) 316 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 317 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 318 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 319 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 320 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 321 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 322 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 323 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 324 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 325 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 326 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 327 CONFIG_SYS_QMAN_CENA_SIZE) 328 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 329 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 330 331 #define CONFIG_SYS_DPAA_FMAN 332 #define CONFIG_SYS_DPAA_PME 333 /* Default address of microcode for the Linux Fman driver 334 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 335 * ucode is stored after env, so we got 0x120000. 336 */ 337 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 338 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 339 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 340 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 341 342 #define CONFIG_FMAN_ENET 343 #define CONFIG_PHYLIB_10G 344 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 345 346 #define CONFIG_PCI_INDIRECT_BRIDGE 347 348 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 349 #define CONFIG_DOS_PARTITION 350 351 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 352 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 353 #define CONFIG_SYS_TBIPA_VALUE 8 354 #define CONFIG_PHYLIB /* recommended PHY management */ 355 #define CONFIG_ETHPRIME "FM1@DTSEC5" 356 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 357 358 /* 359 * Environment 360 */ 361 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 362 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 363 364 /* 365 * Hardware Watchdog 366 */ 367 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 368 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 369 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 370 371 372 /* 373 * additionnal command line configuration. 374 */ 375 #define CONFIG_CMD_PCI 376 #define CONFIG_CMD_ERRATA 377 378 /* we don't need flash support */ 379 #define CONFIG_SYS_NO_FLASH 380 #undef CONFIG_FLASH_CFI_MTD 381 #undef CONFIG_JFFS2_CMDLINE 382 383 /* 384 * For booting Linux, the board info and command line data 385 * have to be in the first 64 MB of memory, since this is 386 * the maximum mapped by the Linux kernel during initialization. 387 */ 388 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 389 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 390 391 #ifdef CONFIG_CMD_KGDB 392 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 393 #endif 394 395 #define __USB_PHY_TYPE utmi 396 #define CONFIG_USB_EHCI_FSL 397 398 /* 399 * Environment Configuration 400 */ 401 #define CONFIG_ENV_OVERWRITE 402 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 403 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 404 #endif 405 406 #ifndef MTDIDS_DEFAULT 407 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 408 #endif /* MTDIDS_DEFAULT */ 409 410 #ifndef MTDPARTS_DEFAULT 411 # define MTDPARTS_DEFAULT "mtdparts=" \ 412 "fsl_elbc_nand:" \ 413 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 414 #endif /* MTDPARTS_DEFAULT */ 415 416 /* architecture specific default bootargs */ 417 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 418 419 /* FIXME: FDT_ADDR is unspecified */ 420 #define CONFIG_KM_DEF_ENV_CPU \ 421 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 422 "cramfsloadfdt=" \ 423 "cramfsload ${fdt_addr_r} " \ 424 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 425 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 426 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 427 "update=" \ 428 "sf probe 0;sf erase 0 +${filesize};" \ 429 "sf write ${load_addr_r} 0 ${filesize};\0" \ 430 "set_fdthigh=true\0" \ 431 "checkfdt=true\0" \ 432 "" 433 434 #define CONFIG_HW_ENV_SETTINGS \ 435 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 436 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 437 "usb_dr_mode=host\0" 438 439 #define CONFIG_KM_NEW_ENV \ 440 "newenv=sf probe 0;" \ 441 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 442 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 443 444 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 445 #ifndef CONFIG_KM_DEF_ARCH 446 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 447 #endif 448 449 #define CONFIG_EXTRA_ENV_SETTINGS \ 450 CONFIG_KM_DEF_ENV \ 451 CONFIG_KM_DEF_ARCH \ 452 CONFIG_KM_NEW_ENV \ 453 CONFIG_HW_ENV_SETTINGS \ 454 "EEprom_ivm=pca9547:70:9\0" \ 455 "" 456 457 #endif /* _CONFIG_KMP204X_H */ 458