1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 12 13 /* an additionnal option is required for UBI as subpage access is 14 * supported in u-boot */ 15 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 16 17 #define CONFIG_NAND_ECC_BCH 18 19 /* common KM defines */ 20 #include "keymile-common.h" 21 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_RAMBOOT_PBL 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 27 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 28 29 /* High Level Configuration Options */ 30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 31 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 32 #define CONFIG_MP /* support multiple processors */ 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 36 #define CONFIG_PCIE1 /* PCIE controller 1 */ 37 #define CONFIG_PCIE3 /* PCIE controller 3 */ 38 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 39 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 40 41 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 42 43 /* Environment in SPI Flash */ 44 #define CONFIG_SYS_EXTRA_ENV_RELOC 45 #define CONFIG_ENV_SPI_BUS 0 46 #define CONFIG_ENV_SPI_CS 0 47 #define CONFIG_ENV_SPI_MAX_HZ 20000000 48 #define CONFIG_ENV_SPI_MODE 0 49 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 50 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 51 #define CONFIG_ENV_SECT_SIZE 0x010000 52 #define CONFIG_ENV_OFFSET_REDUND 0x110000 53 #define CONFIG_ENV_TOTAL_SIZE 0x020000 54 55 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 56 57 #ifndef __ASSEMBLY__ 58 unsigned long get_board_sys_clk(unsigned long dummy); 59 #endif 60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 61 62 /* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65 #define CONFIG_SYS_CACHE_STASHING 66 #define CONFIG_BACKSIDE_L2_CACHE 67 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 68 #define CONFIG_BTB /* toggle branch predition */ 69 70 #define CONFIG_ENABLE_36BIT_PHYS 71 72 #define CONFIG_ADDR_MAP 73 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 74 75 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 76 77 /* 78 * Config the L3 Cache as L3 SRAM 79 */ 80 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 81 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 82 CONFIG_RAMBOOT_TEXT_BASE) 83 #define CONFIG_SYS_L3_SIZE (1024 << 10) 84 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 85 86 #define CONFIG_SYS_DCSRBAR 0xf0000000 87 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 88 89 /* 90 * DDR Setup 91 */ 92 #define CONFIG_VERY_BIG_RAM 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 97 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 98 99 #define CONFIG_DDR_SPD 100 #define CONFIG_FSL_DDR_INTERACTIVE 101 102 #define CONFIG_SYS_SPD_BUS_NUM 0 103 #define SPD_EEPROM_ADDRESS 0x54 104 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 105 106 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 107 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 108 109 /****************************************************************************** 110 * (PRAM usage) 111 * ... ------------------------------------------------------- 112 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 113 * ... |<------------------- pram -------------------------->| 114 * ... ------------------------------------------------------- 115 * @END_OF_RAM: 116 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 117 * @CONFIG_KM_PHRAM: address for /var 118 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 119 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 120 */ 121 122 /* size of rootfs in RAM */ 123 #define CONFIG_KM_ROOTFSSIZE 0x0 124 /* pseudo-non volatile RAM [hex] */ 125 #define CONFIG_KM_PNVRAM 0x80000 126 /* physical RAM MTD size [hex] */ 127 #define CONFIG_KM_PHRAM 0x100000 128 /* reserved pram area at the end of memory [hex] 129 * u-boot reserves some memory for the MP boot page */ 130 #define CONFIG_KM_RESERVED_PRAM 0x1000 131 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 132 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 133 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 134 135 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 136 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 137 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 138 139 /* 140 * Local Bus Definitions 141 */ 142 143 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 144 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 145 146 /* Nand Flash */ 147 #define CONFIG_NAND_FSL_ELBC 148 #define CONFIG_SYS_NAND_BASE 0xffa00000 149 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 150 151 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 153 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 154 155 /* NAND flash config */ 156 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 157 | BR_PS_8 /* Port Size = 8 bit */ \ 158 | BR_MS_FCM /* MSEL = FCM */ \ 159 | BR_V) /* valid */ 160 161 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 162 | OR_FCM_BCTLD /* LBCTL not ass */ \ 163 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 164 | OR_FCM_RST /* 1 clk read setup */ \ 165 | OR_FCM_PGS /* Large page size */ \ 166 | OR_FCM_CST) /* 0.25 command setup */ 167 168 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 169 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 170 171 /* QRIO FPGA */ 172 #define CONFIG_SYS_QRIO_BASE 0xfb000000 173 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 174 175 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 176 | BR_PS_8 /* Port Size 8 bits */ \ 177 | BR_DECC_OFF /* no error corr */ \ 178 | BR_MS_GPCM /* MSEL = GPCM */ \ 179 | BR_V) /* valid */ 180 181 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 182 | OR_GPCM_BCTLD /* no LCTL assert */ \ 183 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 184 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 185 | OR_GPCM_TRLX /* relaxed tmgs */ \ 186 | OR_GPCM_EAD) /* extra bus clk cycles */ 187 188 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 189 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 190 191 /* bootcounter in QRIO */ 192 #define CONFIG_BOOTCOUNT_LIMIT 193 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 194 195 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 196 #define CONFIG_MISC_INIT_F 197 #define CONFIG_MISC_INIT_R 198 #define CONFIG_LAST_STAGE_INIT 199 200 #define CONFIG_HWCONFIG 201 202 /* define to use L1 as initial stack */ 203 #define CONFIG_L1_INIT_RAM 204 #define CONFIG_SYS_INIT_RAM_LOCK 205 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 206 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 207 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 208 /* The assembler doesn't like typecast */ 209 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 210 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 211 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 213 214 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 215 GENERATED_GBL_DATA_SIZE) 216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 217 218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 219 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 220 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 221 222 /* Serial Port - controlled on board with jumper J8 223 * open - index 2 224 * shorted - index 1 225 */ 226 #define CONFIG_CONS_INDEX 1 227 #define CONFIG_SYS_NS16550_SERIAL 228 #define CONFIG_SYS_NS16550_REG_SIZE 1 229 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 230 231 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 232 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 233 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 234 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 235 236 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 237 238 /* I2C */ 239 240 #define CONFIG_SYS_I2C 241 #define CONFIG_SYS_I2C_INIT_BOARD 242 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 243 #define CONFIG_SYS_NUM_I2C_BUSES 3 244 #define CONFIG_SYS_I2C_MAX_HOPS 1 245 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 246 #define CONFIG_I2C_MULTI_BUS 247 #define CONFIG_I2C_CMD_TREE 248 #define CONFIG_SYS_FSL_I2C_SPEED 400000 249 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 250 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 251 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 252 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 253 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 254 } 255 #ifndef __ASSEMBLY__ 256 void set_sda(int state); 257 void set_scl(int state); 258 int get_sda(void); 259 int get_scl(void); 260 #endif 261 262 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 263 264 /* 265 * eSPI - Enhanced SPI 266 */ 267 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 268 #define CONFIG_SF_DEFAULT_SPEED 20000000 269 #define CONFIG_SF_DEFAULT_MODE 0 270 271 /* 272 * General PCI 273 * Memory space is mapped 1-1, but I/O space must start from 0. 274 */ 275 276 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 277 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 278 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 279 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 280 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 281 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 282 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 283 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 284 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 285 286 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 287 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 288 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 289 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 290 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 291 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 292 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 293 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 294 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 295 296 /* Qman/Bman */ 297 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 298 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 299 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 300 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 301 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 302 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 303 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 304 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 305 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 306 CONFIG_SYS_BMAN_CENA_SIZE) 307 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 308 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 309 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 310 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 311 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 312 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 313 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 314 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 315 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 316 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 317 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 318 CONFIG_SYS_QMAN_CENA_SIZE) 319 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 320 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 321 322 #define CONFIG_SYS_DPAA_FMAN 323 #define CONFIG_SYS_DPAA_PME 324 /* Default address of microcode for the Linux Fman driver 325 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 326 * ucode is stored after env, so we got 0x120000. 327 */ 328 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 329 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 330 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 331 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 332 333 #define CONFIG_FMAN_ENET 334 #define CONFIG_PHYLIB_10G 335 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 336 337 #define CONFIG_PCI_INDIRECT_BRIDGE 338 339 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 340 341 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 342 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 343 #define CONFIG_SYS_TBIPA_VALUE 8 344 #define CONFIG_ETHPRIME "FM1@DTSEC5" 345 346 /* 347 * Environment 348 */ 349 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 350 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 351 352 /* 353 * Hardware Watchdog 354 */ 355 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 356 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 357 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 358 359 360 /* 361 * additionnal command line configuration. 362 */ 363 364 /* we don't need flash support */ 365 #undef CONFIG_FLASH_CFI_MTD 366 #undef CONFIG_JFFS2_CMDLINE 367 368 /* 369 * For booting Linux, the board info and command line data 370 * have to be in the first 64 MB of memory, since this is 371 * the maximum mapped by the Linux kernel during initialization. 372 */ 373 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 374 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 375 376 #ifdef CONFIG_CMD_KGDB 377 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 378 #endif 379 380 #define __USB_PHY_TYPE utmi 381 #define CONFIG_USB_EHCI_FSL 382 383 /* 384 * Environment Configuration 385 */ 386 #define CONFIG_ENV_OVERWRITE 387 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 388 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 389 #endif 390 391 /* architecture specific default bootargs */ 392 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 393 394 /* FIXME: FDT_ADDR is unspecified */ 395 #define CONFIG_KM_DEF_ENV_CPU \ 396 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 397 "cramfsloadfdt=" \ 398 "cramfsload ${fdt_addr_r} " \ 399 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 400 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 401 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 402 "update=" \ 403 "sf probe 0;sf erase 0 +${filesize};" \ 404 "sf write ${load_addr_r} 0 ${filesize};\0" \ 405 "set_fdthigh=true\0" \ 406 "checkfdt=true\0" \ 407 "" 408 409 #define CONFIG_HW_ENV_SETTINGS \ 410 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 411 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 412 "usb_dr_mode=host\0" 413 414 #define CONFIG_KM_NEW_ENV \ 415 "newenv=sf probe 0;" \ 416 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 417 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 418 419 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 420 #ifndef CONFIG_KM_DEF_ARCH 421 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 422 #endif 423 424 #define CONFIG_EXTRA_ENV_SETTINGS \ 425 CONFIG_KM_DEF_ENV \ 426 CONFIG_KM_DEF_ARCH \ 427 CONFIG_KM_NEW_ENV \ 428 CONFIG_HW_ENV_SETTINGS \ 429 "EEprom_ivm=pca9547:70:9\0" \ 430 "" 431 432 #endif /* _CONFIG_KMP204X_H */ 433