1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_PHYS_64BIT 12 #define CONFIG_PPC_P2041 13 14 #define CONFIG_SYS_TEXT_BASE 0xfff80000 15 16 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 17 18 #define CONFIG_NAND_ECC_BCH 19 20 /* common KM defines */ 21 #include "keymile-common.h" 22 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_RAMBOOT_PBL 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg 28 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 32 #define CONFIG_E500 /* BOOKE e500 family */ 33 #define CONFIG_E500MC /* BOOKE e500mc family */ 34 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 35 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 36 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 37 #define CONFIG_MP /* support multiple processors */ 38 39 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 40 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 41 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 42 #define CONFIG_PCI /* Enable PCI/PCIE */ 43 #define CONFIG_PCIE1 /* PCIE controler 1 */ 44 #define CONFIG_PCIE3 /* PCIE controler 3 */ 45 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 46 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 47 48 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 49 50 #define CONFIG_FSL_LAW /* Use common FSL init code */ 51 52 /* Environment in SPI Flash */ 53 #define CONFIG_SYS_EXTRA_ENV_RELOC 54 #define CONFIG_ENV_IS_IN_SPI_FLASH 55 #define CONFIG_ENV_SPI_BUS 0 56 #define CONFIG_ENV_SPI_CS 0 57 #define CONFIG_ENV_SPI_MAX_HZ 20000000 58 #define CONFIG_ENV_SPI_MODE 0 59 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 60 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 61 #define CONFIG_ENV_SECT_SIZE 0x010000 62 #define CONFIG_ENV_OFFSET_REDUND 0x110000 63 #define CONFIG_ENV_TOTAL_SIZE 0x020000 64 65 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 66 67 #ifndef __ASSEMBLY__ 68 unsigned long get_board_sys_clk(unsigned long dummy); 69 #endif 70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 71 72 /* 73 * These can be toggled for performance analysis, otherwise use default. 74 */ 75 #define CONFIG_SYS_CACHE_STASHING 76 #define CONFIG_BACKSIDE_L2_CACHE 77 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 78 #define CONFIG_BTB /* toggle branch predition */ 79 80 #define CONFIG_ENABLE_36BIT_PHYS 81 82 #define CONFIG_ADDR_MAP 83 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 84 85 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 86 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 87 #define CONFIG_SYS_MEMTEST_END 0x00800000 88 #define CONFIG_SYS_ALT_MEMTEST 89 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 90 91 /* 92 * Config the L3 Cache as L3 SRAM 93 */ 94 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 95 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 96 CONFIG_RAMBOOT_TEXT_BASE) 97 #define CONFIG_SYS_L3_SIZE (1024 << 10) 98 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 99 100 #define CONFIG_SYS_DCSRBAR 0xf0000000 101 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 102 103 /* 104 * DDR Setup 105 */ 106 #define CONFIG_VERY_BIG_RAM 107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 109 110 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 111 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 112 113 #define CONFIG_DDR_SPD 114 #define CONFIG_FSL_DDR3 115 #define CONFIG_FSL_DDR_INTERACTIVE 116 117 #define CONFIG_SYS_SPD_BUS_NUM 0 118 #define SPD_EEPROM_ADDRESS 0x54 119 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 120 121 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 123 124 /****************************************************************************** 125 * (PRAM usage) 126 * ... ------------------------------------------------------- 127 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 128 * ... |<------------------- pram -------------------------->| 129 * ... ------------------------------------------------------- 130 * @END_OF_RAM: 131 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 132 * @CONFIG_KM_PHRAM: address for /var 133 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 134 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 135 */ 136 137 /* size of rootfs in RAM */ 138 #define CONFIG_KM_ROOTFSSIZE 0x0 139 /* pseudo-non volatile RAM [hex] */ 140 #define CONFIG_KM_PNVRAM 0x80000 141 /* physical RAM MTD size [hex] */ 142 #define CONFIG_KM_PHRAM 0x100000 143 /* resereved pram area at the end of memroy [hex] */ 144 #define CONFIG_KM_RESERVED_PRAM 0x0 145 /* enable protected RAM */ 146 #define CONFIG_PRAM 0 147 148 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 149 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 150 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 151 152 #define CONFIG_BOOTCOUNT_LIMIT 153 154 /* 155 * Local Bus Definitions 156 */ 157 158 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 159 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 160 161 /* Nand Flash */ 162 #define CONFIG_NAND_FSL_ELBC 163 #define CONFIG_SYS_NAND_BASE 0xffa00000 164 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 165 166 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 167 #define CONFIG_SYS_MAX_NAND_DEVICE 1 168 #define CONFIG_MTD_NAND_VERIFY_WRITE 169 #define CONFIG_CMD_NAND 170 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 171 172 #define CONFIG_BCH 173 174 /* NAND flash config */ 175 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 176 | BR_PS_8 /* Port Size = 8 bit */ \ 177 | BR_MS_FCM /* MSEL = FCM */ \ 178 | BR_V) /* valid */ 179 180 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 181 | OR_FCM_BCTLD /* LBCTL not ass */ \ 182 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 183 | OR_FCM_RST /* 1 clk read setup */ \ 184 | OR_FCM_PGS /* Large page size */ \ 185 | OR_FCM_CST) /* 0.25 command setup */ 186 187 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 188 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 189 190 /* QRIO FPGA */ 191 #define CONFIG_SYS_QRIO_BASE 0xfb000000 192 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 193 194 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 195 | BR_PS_8 /* Port Size 8 bits */ \ 196 | BR_DECC_OFF /* no error corr */ \ 197 | BR_MS_GPCM /* MSEL = GPCM */ \ 198 | BR_V) /* valid */ 199 200 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 201 | OR_GPCM_BCTLD /* no LCTL assert */ \ 202 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 203 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 204 | OR_GPCM_TRLX /* relaxed tmgs */ \ 205 | OR_GPCM_EAD) /* extra bus clk cycles */ 206 207 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 208 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 209 210 #define CONFIG_BOARD_EARLY_INIT_F 211 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 212 #define CONFIG_MISC_INIT_R 213 #define CONFIG_LAST_STAGE_INIT 214 215 #define CONFIG_HWCONFIG 216 217 /* define to use L1 as initial stack */ 218 #define CONFIG_L1_INIT_RAM 219 #define CONFIG_SYS_INIT_RAM_LOCK 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 222 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 223 /* The assembler doesn't like typecast */ 224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 225 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 226 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 227 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 228 229 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 230 GENERATED_GBL_DATA_SIZE) 231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 232 233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 234 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 235 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 236 237 /* Serial Port - controlled on board with jumper J8 238 * open - index 2 239 * shorted - index 1 240 */ 241 #define CONFIG_CONS_INDEX 1 242 #define CONFIG_SYS_NS16550 243 #define CONFIG_SYS_NS16550_SERIAL 244 #define CONFIG_SYS_NS16550_REG_SIZE 1 245 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 246 247 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 248 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 249 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 250 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 251 252 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 253 254 /* Use the HUSH parser */ 255 #define CONFIG_SYS_HUSH_PARSER 256 257 /* pass open firmware flat tree */ 258 #define CONFIG_OF_LIBFDT 259 #define CONFIG_OF_BOARD_SETUP 260 #define CONFIG_OF_STDOUT_VIA_ALIAS 261 262 /* new uImage format support */ 263 #define CONFIG_FIT 264 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 265 266 /* I2C */ 267 #define CONFIG_SYS_I2C 268 #define CONFIG_SYS_NUM_I2C_BUSES 3 269 #define CONFIG_SYS_I2C_MAX_HOPS 1 270 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 271 #define CONFIG_I2C_MULTI_BUS 272 #define CONFIG_I2C_CMD_TREE 273 #define CONFIG_SYS_FSL_I2C_SPEED 400000 274 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 275 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 276 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 277 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 278 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 279 } 280 281 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 282 283 /* 284 * eSPI - Enhanced SPI 285 */ 286 #define CONFIG_FSL_ESPI 287 #define CONFIG_SPI_FLASH 288 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 289 #define CONFIG_SPI_FLASH_STMICRO 290 #define CONFIG_CMD_SF 291 #define CONFIG_SF_DEFAULT_SPEED 20000000 292 #define CONFIG_SF_DEFAULT_MODE 0 293 294 /* 295 * General PCI 296 * Memory space is mapped 1-1, but I/O space must start from 0. 297 */ 298 299 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 300 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 301 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 302 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 303 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 304 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 305 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 306 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 307 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 308 309 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 310 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 311 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 312 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 313 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 314 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 315 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 316 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 317 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 318 319 /* Qman/Bman */ 320 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 321 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 322 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 323 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 324 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 325 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 326 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 327 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 328 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 329 330 #define CONFIG_SYS_DPAA_FMAN 331 #define CONFIG_SYS_DPAA_PME 332 /* Default address of microcode for the Linux Fman driver 333 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 334 * ucode is stored after env, so we got 0x120000. 335 */ 336 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 337 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x120000 338 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 339 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 340 341 #define CONFIG_FMAN_ENET 342 #define CONFIG_PHYLIB_10G 343 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 344 345 #define CONFIG_PCI_INDIRECT_BRIDGE 346 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 347 #define CONFIG_E1000 348 349 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 350 #define CONFIG_DOS_PARTITION 351 352 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 353 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 354 #define CONFIG_SYS_TBIPA_VALUE 8 355 #define CONFIG_PHYLIB /* recommended PHY management */ 356 #define CONFIG_ETHPRIME "FM1@DTSEC5" 357 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 358 359 /* 360 * Environment 361 */ 362 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 363 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 364 365 /* 366 * additionnal command line configuration. 367 */ 368 #define CONFIG_CMD_PCI 369 #define CONFIG_CMD_NET 370 371 /* we don't need flash support */ 372 #define CONFIG_SYS_NO_FLASH 373 #undef CONFIG_CMD_IMLS 374 #undef CONFIG_CMD_FLASH 375 #undef CONFIG_FLASH_CFI_MTD 376 #undef CONFIG_JFFS2_CMDLINE 377 378 /* 379 * For booting Linux, the board info and command line data 380 * have to be in the first 64 MB of memory, since this is 381 * the maximum mapped by the Linux kernel during initialization. 382 */ 383 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 384 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 385 386 #ifdef CONFIG_CMD_KGDB 387 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 388 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 389 #endif 390 391 #define __USB_PHY_TYPE utmi 392 393 /* 394 * Environment Configuration 395 */ 396 #define CONFIG_ENV_OVERWRITE 397 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 398 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 399 #endif 400 401 #ifndef MTDIDS_DEFAULT 402 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 403 #endif /* MTDIDS_DEFAULT */ 404 405 #ifndef MTDPARTS_DEFAULT 406 # define MTDPARTS_DEFAULT "mtdparts=" \ 407 "fsl_elbc_nand:" \ 408 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 409 #endif /* MTDPARTS_DEFAULT */ 410 411 /* architecture specific default bootargs */ 412 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 413 414 /* FIXME: FDT_ADDR is unspecified */ 415 #define CONFIG_KM_DEF_ENV_CPU \ 416 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 417 "cramfsloadfdt=" \ 418 "cramfsload ${fdt_addr_r} " \ 419 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 420 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 421 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 422 "update=" \ 423 "sf probe 0;sf erase 0 +${filesize};" \ 424 "sf write ${load_addr_r} 0 ${filesize};\0" \ 425 "" 426 427 #define CONFIG_HW_ENV_SETTINGS \ 428 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 429 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 430 "usb_dr_mode=host\0" 431 432 #define CONFIG_KM_NEW_ENV \ 433 "newenv=sf probe 0;" \ 434 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 435 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 436 437 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 438 #ifndef CONFIG_KM_DEF_ARCH 439 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 440 #endif 441 442 #define CONFIG_EXTRA_ENV_SETTINGS \ 443 CONFIG_KM_DEF_ENV \ 444 CONFIG_KM_DEF_ARCH \ 445 CONFIG_KM_NEW_ENV \ 446 CONFIG_HW_ENV_SETTINGS \ 447 "EEprom_ivm=pca9547:70:9\0" \ 448 "" 449 450 #endif /* _CONFIG_KMP204X_H */ 451