1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 Keymile AG 4 * Valentin Longchamp <valentin.longchamp@keymile.com> 5 */ 6 7 #ifndef _CONFIG_KMP204X_H 8 #define _CONFIG_KMP204X_H 9 10 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 11 12 /* an additionnal option is required for UBI as subpage access is 13 * supported in u-boot */ 14 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 15 16 #define CONFIG_NAND_ECC_BCH 17 18 /* common KM defines */ 19 #include "keymile-common.h" 20 21 #define CONFIG_SYS_RAMBOOT 22 #define CONFIG_RAMBOOT_PBL 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 26 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 30 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 31 32 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 33 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 34 #define CONFIG_PCIE1 /* PCIE controller 1 */ 35 #define CONFIG_PCIE3 /* PCIE controller 3 */ 36 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 37 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 38 39 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 40 41 /* Environment in SPI Flash */ 42 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 43 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 44 #define CONFIG_ENV_SECT_SIZE 0x010000 45 #define CONFIG_ENV_OFFSET_REDUND 0x110000 46 #define CONFIG_ENV_TOTAL_SIZE 0x020000 47 48 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 49 50 #ifndef __ASSEMBLY__ 51 unsigned long get_board_sys_clk(unsigned long dummy); 52 #endif 53 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 54 55 /* 56 * These can be toggled for performance analysis, otherwise use default. 57 */ 58 #define CONFIG_SYS_CACHE_STASHING 59 #define CONFIG_BACKSIDE_L2_CACHE 60 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 61 #define CONFIG_BTB /* toggle branch predition */ 62 63 #define CONFIG_ENABLE_36BIT_PHYS 64 65 #define CONFIG_ADDR_MAP 66 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 67 68 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 69 70 /* 71 * Config the L3 Cache as L3 SRAM 72 */ 73 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 74 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 75 CONFIG_RAMBOOT_TEXT_BASE) 76 #define CONFIG_SYS_L3_SIZE (1024 << 10) 77 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 78 79 #define CONFIG_SYS_DCSRBAR 0xf0000000 80 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 81 82 /* 83 * DDR Setup 84 */ 85 #define CONFIG_VERY_BIG_RAM 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 90 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 91 92 #define CONFIG_DDR_SPD 93 94 #define CONFIG_SYS_SPD_BUS_NUM 0 95 #define SPD_EEPROM_ADDRESS 0x54 96 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 97 98 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 99 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 100 101 /****************************************************************************** 102 * (PRAM usage) 103 * ... ------------------------------------------------------- 104 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 105 * ... |<------------------- pram -------------------------->| 106 * ... ------------------------------------------------------- 107 * @END_OF_RAM: 108 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 109 * @CONFIG_KM_PHRAM: address for /var 110 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 111 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 112 */ 113 114 /* size of rootfs in RAM */ 115 #define CONFIG_KM_ROOTFSSIZE 0x0 116 /* pseudo-non volatile RAM [hex] */ 117 #define CONFIG_KM_PNVRAM 0x80000 118 /* physical RAM MTD size [hex] */ 119 #define CONFIG_KM_PHRAM 0x100000 120 /* reserved pram area at the end of memory [hex] 121 * u-boot reserves some memory for the MP boot page */ 122 #define CONFIG_KM_RESERVED_PRAM 0x1000 123 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 124 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 125 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 126 127 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 128 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 129 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 130 131 /* 132 * Local Bus Definitions 133 */ 134 135 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 136 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 137 138 /* Nand Flash */ 139 #define CONFIG_NAND_FSL_ELBC 140 #define CONFIG_SYS_NAND_BASE 0xffa00000 141 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 142 143 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 145 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 146 147 /* NAND flash config */ 148 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 149 | BR_PS_8 /* Port Size = 8 bit */ \ 150 | BR_MS_FCM /* MSEL = FCM */ \ 151 | BR_V) /* valid */ 152 153 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 154 | OR_FCM_BCTLD /* LBCTL not ass */ \ 155 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 156 | OR_FCM_RST /* 1 clk read setup */ \ 157 | OR_FCM_PGS /* Large page size */ \ 158 | OR_FCM_CST) /* 0.25 command setup */ 159 160 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 161 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 162 163 /* QRIO FPGA */ 164 #define CONFIG_SYS_QRIO_BASE 0xfb000000 165 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 166 167 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 168 | BR_PS_8 /* Port Size 8 bits */ \ 169 | BR_DECC_OFF /* no error corr */ \ 170 | BR_MS_GPCM /* MSEL = GPCM */ \ 171 | BR_V) /* valid */ 172 173 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 174 | OR_GPCM_BCTLD /* no LCTL assert */ \ 175 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 176 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 177 | OR_GPCM_TRLX /* relaxed tmgs */ \ 178 | OR_GPCM_EAD) /* extra bus clk cycles */ 179 180 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 181 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 182 183 #define CONFIG_MISC_INIT_F 184 185 #define CONFIG_HWCONFIG 186 187 /* define to use L1 as initial stack */ 188 #define CONFIG_L1_INIT_RAM 189 #define CONFIG_SYS_INIT_RAM_LOCK 190 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 192 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 193 /* The assembler doesn't like typecast */ 194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 195 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 196 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 197 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 198 199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 200 GENERATED_GBL_DATA_SIZE) 201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 202 203 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 204 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 205 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 206 207 /* Serial Port - controlled on board with jumper J8 208 * open - index 2 209 * shorted - index 1 210 */ 211 #define CONFIG_SYS_NS16550_SERIAL 212 #define CONFIG_SYS_NS16550_REG_SIZE 1 213 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 214 215 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 216 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 217 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 218 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 219 220 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 221 222 /* I2C */ 223 224 #define CONFIG_SYS_I2C 225 #define CONFIG_SYS_I2C_INIT_BOARD 226 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 227 #define CONFIG_SYS_NUM_I2C_BUSES 3 228 #define CONFIG_SYS_I2C_MAX_HOPS 1 229 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 230 #define CONFIG_I2C_MULTI_BUS 231 #define CONFIG_I2C_CMD_TREE 232 #define CONFIG_SYS_FSL_I2C_SPEED 400000 233 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 234 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 235 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 236 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 237 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 238 } 239 #ifndef __ASSEMBLY__ 240 void set_sda(int state); 241 void set_scl(int state); 242 int get_sda(void); 243 int get_scl(void); 244 #endif 245 246 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 247 248 /* 249 * eSPI - Enhanced SPI 250 */ 251 252 /* 253 * General PCI 254 * Memory space is mapped 1-1, but I/O space must start from 0. 255 */ 256 257 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 258 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 259 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 260 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 261 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 262 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 263 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 264 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 265 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 266 267 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 268 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 269 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 270 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 271 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 272 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 273 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 274 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 275 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 276 277 /* Qman/Bman */ 278 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 279 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 280 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 281 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 282 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 283 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 284 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 285 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 286 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 287 CONFIG_SYS_BMAN_CENA_SIZE) 288 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 289 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 290 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 291 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 292 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 293 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 294 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 295 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 296 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 297 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 298 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 299 CONFIG_SYS_QMAN_CENA_SIZE) 300 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 301 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 302 303 #define CONFIG_SYS_DPAA_FMAN 304 #define CONFIG_SYS_DPAA_PME 305 /* Default address of microcode for the Linux Fman driver 306 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 307 * ucode is stored after env, so we got 0x120000. 308 */ 309 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 310 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 311 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 312 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 313 314 #define CONFIG_FMAN_ENET 315 #define CONFIG_PHYLIB_10G 316 317 #define CONFIG_PCI_INDIRECT_BRIDGE 318 319 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 320 321 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 322 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 323 #define CONFIG_SYS_TBIPA_VALUE 8 324 #define CONFIG_ETHPRIME "FM1@DTSEC5" 325 326 /* 327 * Environment 328 */ 329 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 330 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 331 332 /* 333 * Hardware Watchdog 334 */ 335 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 336 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 337 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 338 339 340 /* 341 * additionnal command line configuration. 342 */ 343 344 /* we don't need flash support */ 345 #undef CONFIG_JFFS2_CMDLINE 346 347 /* 348 * For booting Linux, the board info and command line data 349 * have to be in the first 64 MB of memory, since this is 350 * the maximum mapped by the Linux kernel during initialization. 351 */ 352 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 353 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 354 355 #ifdef CONFIG_CMD_KGDB 356 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 357 #endif 358 359 #define __USB_PHY_TYPE utmi 360 #define CONFIG_USB_EHCI_FSL 361 362 /* 363 * Environment Configuration 364 */ 365 #define CONFIG_ENV_OVERWRITE 366 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 367 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 368 #endif 369 370 /* architecture specific default bootargs */ 371 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 372 373 /* FIXME: FDT_ADDR is unspecified */ 374 #define CONFIG_KM_DEF_ENV_CPU \ 375 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 376 "cramfsloadfdt=" \ 377 "cramfsload ${fdt_addr_r} " \ 378 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 379 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 380 "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0" \ 381 "update=" \ 382 "sf probe 0;sf erase 0 +${filesize};" \ 383 "sf write ${load_addr_r} 0 ${filesize};\0" \ 384 "set_fdthigh=true\0" \ 385 "checkfdt=true\0" \ 386 "" 387 388 #define CONFIG_HW_ENV_SETTINGS \ 389 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 390 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 391 "usb_dr_mode=host\0" 392 393 #define CONFIG_KM_NEW_ENV \ 394 "newenv=sf probe 0;" \ 395 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 396 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 397 398 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 399 #ifndef CONFIG_KM_DEF_ARCH 400 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 401 #endif 402 403 #define CONFIG_EXTRA_ENV_SETTINGS \ 404 CONFIG_KM_DEF_ENV \ 405 CONFIG_KM_DEF_ARCH \ 406 CONFIG_KM_NEW_ENV \ 407 CONFIG_HW_ENV_SETTINGS \ 408 "EEprom_ivm=pca9547:70:9\0" \ 409 "" 410 411 #endif /* _CONFIG_KMP204X_H */ 412