1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_PHYS_64BIT 12 #define CONFIG_PPC_P2041 13 14 #define CONFIG_SYS_TEXT_BASE 0xfff80000 15 16 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 17 18 /* an additionnal option is required for UBI as subpage access is 19 * supported in u-boot */ 20 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 21 22 #define CONFIG_NAND_ECC_BCH 23 24 /* common KM defines */ 25 #include "keymile-common.h" 26 27 #define CONFIG_SYS_RAMBOOT 28 #define CONFIG_RAMBOOT_PBL 29 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 31 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 32 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 36 #define CONFIG_E500 /* BOOKE e500 family */ 37 #define CONFIG_E500MC /* BOOKE e500mc family */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 40 #define CONFIG_MP /* support multiple processors */ 41 42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 43 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 44 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 45 #define CONFIG_PCI /* Enable PCI/PCIE */ 46 #define CONFIG_PCIE1 /* PCIE controler 1 */ 47 #define CONFIG_PCIE3 /* PCIE controler 3 */ 48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 49 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 50 51 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 52 53 #define CONFIG_FSL_LAW /* Use common FSL init code */ 54 55 /* Environment in SPI Flash */ 56 #define CONFIG_SYS_EXTRA_ENV_RELOC 57 #define CONFIG_ENV_IS_IN_SPI_FLASH 58 #define CONFIG_ENV_SPI_BUS 0 59 #define CONFIG_ENV_SPI_CS 0 60 #define CONFIG_ENV_SPI_MAX_HZ 20000000 61 #define CONFIG_ENV_SPI_MODE 0 62 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 63 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 64 #define CONFIG_ENV_SECT_SIZE 0x010000 65 #define CONFIG_ENV_OFFSET_REDUND 0x110000 66 #define CONFIG_ENV_TOTAL_SIZE 0x020000 67 68 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 69 70 #ifndef __ASSEMBLY__ 71 unsigned long get_board_sys_clk(unsigned long dummy); 72 #endif 73 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 74 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_SYS_CACHE_STASHING 79 #define CONFIG_BACKSIDE_L2_CACHE 80 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 81 #define CONFIG_BTB /* toggle branch predition */ 82 83 #define CONFIG_ENABLE_36BIT_PHYS 84 85 #define CONFIG_ADDR_MAP 86 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 87 88 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 89 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 90 #define CONFIG_SYS_MEMTEST_END 0x00800000 91 #define CONFIG_SYS_ALT_MEMTEST 92 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 93 94 /* 95 * Config the L3 Cache as L3 SRAM 96 */ 97 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 98 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 99 CONFIG_RAMBOOT_TEXT_BASE) 100 #define CONFIG_SYS_L3_SIZE (1024 << 10) 101 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 102 103 #define CONFIG_SYS_DCSRBAR 0xf0000000 104 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 105 106 /* 107 * DDR Setup 108 */ 109 #define CONFIG_VERY_BIG_RAM 110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 112 113 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 114 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 115 116 #define CONFIG_DDR_SPD 117 #define CONFIG_SYS_FSL_DDR3 118 #define CONFIG_FSL_DDR_INTERACTIVE 119 120 #define CONFIG_SYS_SPD_BUS_NUM 0 121 #define SPD_EEPROM_ADDRESS 0x54 122 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 123 124 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 126 127 /****************************************************************************** 128 * (PRAM usage) 129 * ... ------------------------------------------------------- 130 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 131 * ... |<------------------- pram -------------------------->| 132 * ... ------------------------------------------------------- 133 * @END_OF_RAM: 134 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 135 * @CONFIG_KM_PHRAM: address for /var 136 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 137 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 138 */ 139 140 /* size of rootfs in RAM */ 141 #define CONFIG_KM_ROOTFSSIZE 0x0 142 /* pseudo-non volatile RAM [hex] */ 143 #define CONFIG_KM_PNVRAM 0x80000 144 /* physical RAM MTD size [hex] */ 145 #define CONFIG_KM_PHRAM 0x100000 146 /* resereved pram area at the end of memroy [hex] */ 147 #define CONFIG_KM_RESERVED_PRAM 0x0 148 /* enable protected RAM */ 149 #define CONFIG_PRAM 0 150 151 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 152 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 153 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 154 155 /* 156 * Local Bus Definitions 157 */ 158 159 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 160 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 161 162 /* Nand Flash */ 163 #define CONFIG_NAND_FSL_ELBC 164 #define CONFIG_SYS_NAND_BASE 0xffa00000 165 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 166 167 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 168 #define CONFIG_SYS_MAX_NAND_DEVICE 1 169 #define CONFIG_MTD_NAND_VERIFY_WRITE 170 #define CONFIG_CMD_NAND 171 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 172 173 #define CONFIG_BCH 174 175 /* NAND flash config */ 176 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 177 | BR_PS_8 /* Port Size = 8 bit */ \ 178 | BR_MS_FCM /* MSEL = FCM */ \ 179 | BR_V) /* valid */ 180 181 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 182 | OR_FCM_BCTLD /* LBCTL not ass */ \ 183 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 184 | OR_FCM_RST /* 1 clk read setup */ \ 185 | OR_FCM_PGS /* Large page size */ \ 186 | OR_FCM_CST) /* 0.25 command setup */ 187 188 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 189 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 190 191 /* QRIO FPGA */ 192 #define CONFIG_SYS_QRIO_BASE 0xfb000000 193 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 194 195 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 196 | BR_PS_8 /* Port Size 8 bits */ \ 197 | BR_DECC_OFF /* no error corr */ \ 198 | BR_MS_GPCM /* MSEL = GPCM */ \ 199 | BR_V) /* valid */ 200 201 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 202 | OR_GPCM_BCTLD /* no LCTL assert */ \ 203 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 204 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 205 | OR_GPCM_TRLX /* relaxed tmgs */ \ 206 | OR_GPCM_EAD) /* extra bus clk cycles */ 207 208 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 209 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 210 211 /* bootcounter in QRIO */ 212 #define CONFIG_BOOTCOUNT_LIMIT 213 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 214 215 #define CONFIG_BOARD_EARLY_INIT_F 216 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 217 #define CONFIG_MISC_INIT_F 218 #define CONFIG_MISC_INIT_R 219 #define CONFIG_LAST_STAGE_INIT 220 221 #define CONFIG_HWCONFIG 222 223 /* define to use L1 as initial stack */ 224 #define CONFIG_L1_INIT_RAM 225 #define CONFIG_SYS_INIT_RAM_LOCK 226 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 229 /* The assembler doesn't like typecast */ 230 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 231 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 232 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 233 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 234 235 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 236 GENERATED_GBL_DATA_SIZE) 237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 238 239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 240 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 241 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 242 243 /* Serial Port - controlled on board with jumper J8 244 * open - index 2 245 * shorted - index 1 246 */ 247 #define CONFIG_CONS_INDEX 1 248 #define CONFIG_SYS_NS16550 249 #define CONFIG_SYS_NS16550_SERIAL 250 #define CONFIG_SYS_NS16550_REG_SIZE 1 251 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 252 253 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 254 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 255 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 256 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 257 258 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 259 260 /* Use the HUSH parser */ 261 #define CONFIG_SYS_HUSH_PARSER 262 263 /* pass open firmware flat tree */ 264 #define CONFIG_OF_LIBFDT 265 #define CONFIG_OF_BOARD_SETUP 266 #define CONFIG_OF_STDOUT_VIA_ALIAS 267 268 /* new uImage format support */ 269 #define CONFIG_FIT 270 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 271 272 /* I2C */ 273 274 #define CONFIG_SYS_I2C 275 #define CONFIG_SYS_I2C_INIT_BOARD 276 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 277 #define CONFIG_SYS_NUM_I2C_BUSES 3 278 #define CONFIG_SYS_I2C_MAX_HOPS 1 279 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 280 #define CONFIG_I2C_MULTI_BUS 281 #define CONFIG_I2C_CMD_TREE 282 #define CONFIG_SYS_FSL_I2C_SPEED 400000 283 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 284 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 285 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 286 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 287 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 288 } 289 #ifndef __ASSEMBLY__ 290 void set_sda(int state); 291 void set_scl(int state); 292 int get_sda(void); 293 int get_scl(void); 294 #endif 295 296 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 297 298 /* 299 * eSPI - Enhanced SPI 300 */ 301 #define CONFIG_FSL_ESPI 302 #define CONFIG_SPI_FLASH 303 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 304 #define CONFIG_SPI_FLASH_STMICRO 305 #define CONFIG_SPI_FLASH_SPANSION 306 #define CONFIG_CMD_SF 307 #define CONFIG_SF_DEFAULT_SPEED 20000000 308 #define CONFIG_SF_DEFAULT_MODE 0 309 310 /* 311 * General PCI 312 * Memory space is mapped 1-1, but I/O space must start from 0. 313 */ 314 315 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 316 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 317 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 318 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 319 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 320 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 321 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 322 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 323 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 324 325 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 326 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 327 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 328 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 329 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 330 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 331 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 332 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 333 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 334 335 /* Qman/Bman */ 336 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 337 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 338 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 339 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 340 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 341 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 342 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 343 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 344 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 345 346 #define CONFIG_SYS_DPAA_FMAN 347 #define CONFIG_SYS_DPAA_PME 348 /* Default address of microcode for the Linux Fman driver 349 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 350 * ucode is stored after env, so we got 0x120000. 351 */ 352 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 353 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x120000 354 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 355 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 356 357 #define CONFIG_FMAN_ENET 358 #define CONFIG_PHYLIB_10G 359 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 360 361 #define CONFIG_PCI_INDIRECT_BRIDGE 362 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 363 #define CONFIG_E1000 364 365 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 366 #define CONFIG_DOS_PARTITION 367 368 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 369 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 370 #define CONFIG_SYS_TBIPA_VALUE 8 371 #define CONFIG_PHYLIB /* recommended PHY management */ 372 #define CONFIG_ETHPRIME "FM1@DTSEC5" 373 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 374 375 /* 376 * Environment 377 */ 378 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 379 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 380 381 /* 382 * additionnal command line configuration. 383 */ 384 #define CONFIG_CMD_PCI 385 #define CONFIG_CMD_NET 386 387 /* we don't need flash support */ 388 #define CONFIG_SYS_NO_FLASH 389 #undef CONFIG_CMD_IMLS 390 #undef CONFIG_CMD_FLASH 391 #undef CONFIG_FLASH_CFI_MTD 392 #undef CONFIG_JFFS2_CMDLINE 393 394 /* 395 * For booting Linux, the board info and command line data 396 * have to be in the first 64 MB of memory, since this is 397 * the maximum mapped by the Linux kernel during initialization. 398 */ 399 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 400 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 401 402 #ifdef CONFIG_CMD_KGDB 403 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 404 #endif 405 406 #define __USB_PHY_TYPE utmi 407 408 /* 409 * Environment Configuration 410 */ 411 #define CONFIG_ENV_OVERWRITE 412 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 413 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 414 #endif 415 416 #ifndef MTDIDS_DEFAULT 417 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 418 #endif /* MTDIDS_DEFAULT */ 419 420 #ifndef MTDPARTS_DEFAULT 421 # define MTDPARTS_DEFAULT "mtdparts=" \ 422 "fsl_elbc_nand:" \ 423 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 424 #endif /* MTDPARTS_DEFAULT */ 425 426 /* architecture specific default bootargs */ 427 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 428 429 /* FIXME: FDT_ADDR is unspecified */ 430 #define CONFIG_KM_DEF_ENV_CPU \ 431 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 432 "cramfsloadfdt=" \ 433 "cramfsload ${fdt_addr_r} " \ 434 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 435 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 436 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 437 "update=" \ 438 "sf probe 0;sf erase 0 +${filesize};" \ 439 "sf write ${load_addr_r} 0 ${filesize};\0" \ 440 "set_fdthigh=true\0" \ 441 "" 442 443 #define CONFIG_HW_ENV_SETTINGS \ 444 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 445 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 446 "usb_dr_mode=host\0" 447 448 #define CONFIG_KM_NEW_ENV \ 449 "newenv=sf probe 0;" \ 450 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 451 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 452 453 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 454 #ifndef CONFIG_KM_DEF_ARCH 455 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 456 #endif 457 458 #define CONFIG_EXTRA_ENV_SETTINGS \ 459 CONFIG_KM_DEF_ENV \ 460 CONFIG_KM_DEF_ARCH \ 461 CONFIG_KM_NEW_ENV \ 462 CONFIG_HW_ENV_SETTINGS \ 463 "EEprom_ivm=pca9547:70:9\0" \ 464 "" 465 466 #endif /* _CONFIG_KMP204X_H */ 467