1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2013 Keymile AG
4  * Valentin Longchamp <valentin.longchamp@keymile.com>
5  */
6 
7 #ifndef _CONFIG_KMP204X_H
8 #define _CONFIG_KMP204X_H
9 
10 #define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
11 
12 /* an additionnal option is required for UBI as subpage access is
13  * supported in u-boot */
14 #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
15 
16 #define CONFIG_NAND_ECC_BCH
17 
18 /* common KM defines */
19 #include "keymile-common.h"
20 
21 #define CONFIG_SYS_RAMBOOT
22 #define CONFIG_RAMBOOT_PBL
23 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
24 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
25 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
26 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
27 
28 /* High Level Configuration Options */
29 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
30 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
31 
32 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
33 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
34 #define CONFIG_PCIE1			/* PCIE controller 1 */
35 #define CONFIG_PCIE3			/* PCIE controller 3 */
36 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
37 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
38 
39 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
40 
41 /* Environment in SPI Flash */
42 #define CONFIG_ENV_SPI_BUS              0
43 #define CONFIG_ENV_SPI_CS               0
44 #define CONFIG_ENV_SPI_MAX_HZ           20000000
45 #define CONFIG_ENV_SPI_MODE             0
46 #define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
47 #define CONFIG_ENV_SIZE			0x004000	/* 16K env */
48 #define CONFIG_ENV_SECT_SIZE            0x010000
49 #define CONFIG_ENV_OFFSET_REDUND	0x110000
50 #define CONFIG_ENV_TOTAL_SIZE		0x020000
51 
52 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
53 
54 #ifndef __ASSEMBLY__
55 unsigned long get_board_sys_clk(unsigned long dummy);
56 #endif
57 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
58 
59 /*
60  * These can be toggled for performance analysis, otherwise use default.
61  */
62 #define CONFIG_SYS_CACHE_STASHING
63 #define CONFIG_BACKSIDE_L2_CACHE
64 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
65 #define CONFIG_BTB			/* toggle branch predition */
66 
67 #define CONFIG_ENABLE_36BIT_PHYS
68 
69 #define CONFIG_ADDR_MAP
70 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
71 
72 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS	/* POST memory regions test */
73 
74 /*
75  *  Config the L3 Cache as L3 SRAM
76  */
77 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
79 		CONFIG_RAMBOOT_TEXT_BASE)
80 #define CONFIG_SYS_L3_SIZE		(1024 << 10)
81 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
82 
83 #define CONFIG_SYS_DCSRBAR		0xf0000000
84 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
85 
86 /*
87  * DDR Setup
88  */
89 #define CONFIG_VERY_BIG_RAM
90 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
91 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
92 
93 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
94 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
95 
96 #define CONFIG_DDR_SPD
97 #define CONFIG_FSL_DDR_INTERACTIVE
98 
99 #define CONFIG_SYS_SPD_BUS_NUM	0
100 #define SPD_EEPROM_ADDRESS	0x54
101 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
102 
103 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
104 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
105 
106 /******************************************************************************
107  * (PRAM usage)
108  * ... -------------------------------------------------------
109  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
110  * ... |<------------------- pram -------------------------->|
111  * ... -------------------------------------------------------
112  * @END_OF_RAM:
113  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
114  * @CONFIG_KM_PHRAM: address for /var
115  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
116  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
117  */
118 
119 /* size of rootfs in RAM */
120 #define CONFIG_KM_ROOTFSSIZE	0x0
121 /* pseudo-non volatile RAM [hex] */
122 #define CONFIG_KM_PNVRAM	0x80000
123 /* physical RAM MTD size [hex] */
124 #define CONFIG_KM_PHRAM		0x100000
125 /* reserved pram area at the end of memory [hex]
126  * u-boot reserves some memory for the MP boot page */
127 #define CONFIG_KM_RESERVED_PRAM	0x1000
128 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
129  * is not valid yet, which is the case for when u-boot copies itself to RAM */
130 #define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
131 
132 #define CONFIG_KM_CRAMFS_ADDR	0x2000000
133 #define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
134 #define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
135 
136 /*
137  * Local Bus Definitions
138  */
139 
140 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
141 #define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
142 
143 /* Nand Flash */
144 #define CONFIG_NAND_FSL_ELBC
145 #define CONFIG_SYS_NAND_BASE		0xffa00000
146 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
147 
148 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
149 #define CONFIG_SYS_MAX_NAND_DEVICE	1
150 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
151 
152 /* NAND flash config */
153 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
154 			       | BR_PS_8	       /* Port Size = 8 bit */ \
155 			       | BR_MS_FCM	       /* MSEL = FCM */ \
156 			       | BR_V)		       /* valid */
157 
158 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
159 			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
160 			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
161 			       | OR_FCM_RST	/* 1 clk read setup */	\
162 			       | OR_FCM_PGS	/* Large page size */	\
163 			       | OR_FCM_CST)	/* 0.25 command setup */
164 
165 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
166 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
167 
168 /* QRIO FPGA */
169 #define CONFIG_SYS_QRIO_BASE		0xfb000000
170 #define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
171 
172 #define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
173 				| BR_PS_8	/* Port Size 8 bits */ \
174 				| BR_DECC_OFF	/* no error corr */ \
175 				| BR_MS_GPCM	/* MSEL = GPCM */ \
176 				| BR_V)		/* valid */
177 
178 #define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
179 				| OR_GPCM_BCTLD /* no LCTL assert */ \
180 				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
181 				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
182 				| OR_GPCM_TRLX /* relaxed tmgs */ \
183 				| OR_GPCM_EAD) /* extra bus clk cycles */
184 
185 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
186 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
187 
188 #define CONFIG_MISC_INIT_F
189 
190 #define CONFIG_HWCONFIG
191 
192 /* define to use L1 as initial stack */
193 #define CONFIG_L1_INIT_RAM
194 #define CONFIG_SYS_INIT_RAM_LOCK
195 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
198 /* The assembler doesn't like typecast */
199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
200 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
201 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
202 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
203 
204 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
205 					GENERATED_GBL_DATA_SIZE)
206 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
207 
208 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
209 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
210 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
211 
212 /* Serial Port - controlled on board with jumper J8
213  * open - index 2
214  * shorted - index 1
215  */
216 #define CONFIG_SYS_NS16550_SERIAL
217 #define CONFIG_SYS_NS16550_REG_SIZE	1
218 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
219 
220 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
221 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
222 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
223 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
224 
225 #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
226 
227 /* I2C */
228 
229 #define CONFIG_SYS_I2C
230 #define CONFIG_SYS_I2C_INIT_BOARD
231 #define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
232 #define CONFIG_SYS_NUM_I2C_BUSES	3
233 #define CONFIG_SYS_I2C_MAX_HOPS		1
234 #define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
235 #define CONFIG_I2C_MULTI_BUS
236 #define CONFIG_I2C_CMD_TREE
237 #define CONFIG_SYS_FSL_I2C_SPEED	400000
238 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
239 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
240 #define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
241 					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
242 					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
243 				}
244 #ifndef __ASSEMBLY__
245 void set_sda(int state);
246 void set_scl(int state);
247 int get_sda(void);
248 int get_scl(void);
249 #endif
250 
251 #define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
252 
253 /*
254  * eSPI - Enhanced SPI
255  */
256 #define CONFIG_SPI_FLASH_BAR	/* 4 byte-addressing */
257 #define CONFIG_SF_DEFAULT_SPEED         20000000
258 #define CONFIG_SF_DEFAULT_MODE          0
259 
260 /*
261  * General PCI
262  * Memory space is mapped 1-1, but I/O space must start from 0.
263  */
264 
265 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
266 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
267 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
268 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
269 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
270 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
271 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
272 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
273 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
274 
275 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
276 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
277 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
278 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
279 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
280 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
281 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
282 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
283 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
284 
285 /* Qman/Bman */
286 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
287 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
288 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
289 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
290 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
291 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
292 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
293 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
294 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
295 					CONFIG_SYS_BMAN_CENA_SIZE)
296 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
297 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
298 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
299 #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
300 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
301 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
302 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
303 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
304 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
305 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
306 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
307 					CONFIG_SYS_QMAN_CENA_SIZE)
308 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
309 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
310 
311 #define CONFIG_SYS_DPAA_FMAN
312 #define CONFIG_SYS_DPAA_PME
313 /* Default address of microcode for the Linux Fman driver
314  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
315  * ucode is stored after env, so we got 0x120000.
316  */
317 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
318 #define CONFIG_SYS_FMAN_FW_ADDR	0x120000
319 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
320 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
321 
322 #define CONFIG_FMAN_ENET
323 #define CONFIG_PHYLIB_10G
324 
325 #define CONFIG_PCI_INDIRECT_BRIDGE
326 
327 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
328 
329 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
330 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
331 #define CONFIG_SYS_TBIPA_VALUE	8
332 #define CONFIG_ETHPRIME		"FM1@DTSEC5"
333 
334 /*
335  * Environment
336  */
337 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
338 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
339 
340 /*
341  * Hardware Watchdog
342  */
343 #define CONFIG_WATCHDOG			/* enable CPU watchdog */
344 #define CONFIG_WATCHDOG_PRESC 34	/* wdog prescaler 2^(64-34) (~10min) */
345 #define CONFIG_WATCHDOG_RC WRC_CHIP	/* reset chip on watchdog event */
346 
347 
348 /*
349  * additionnal command line configuration.
350  */
351 
352 /* we don't need flash support */
353 #undef CONFIG_FLASH_CFI_MTD
354 #undef CONFIG_JFFS2_CMDLINE
355 
356 /*
357  * For booting Linux, the board info and command line data
358  * have to be in the first 64 MB of memory, since this is
359  * the maximum mapped by the Linux kernel during initialization.
360  */
361 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
362 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
363 
364 #ifdef CONFIG_CMD_KGDB
365 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
366 #endif
367 
368 #define __USB_PHY_TYPE	utmi
369 #define CONFIG_USB_EHCI_FSL
370 
371 /*
372  * Environment Configuration
373  */
374 #define CONFIG_ENV_OVERWRITE
375 #ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
376 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
377 #endif
378 
379 /* architecture specific default bootargs */
380 #define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
381 
382 /* FIXME: FDT_ADDR is unspecified */
383 #define CONFIG_KM_DEF_ENV_CPU						\
384 	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
385 	"cramfsloadfdt="						\
386 		"cramfsload ${fdt_addr_r} "				\
387 		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
388 	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
389 	"u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0"		\
390 	"update="							\
391 		"sf probe 0;sf erase 0 +${filesize};"			\
392 		"sf write ${load_addr_r} 0 ${filesize};\0"		\
393 	"set_fdthigh=true\0"						\
394 	"checkfdt=true\0"						\
395 	""
396 
397 #define CONFIG_HW_ENV_SETTINGS						\
398 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
399 	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
400 	"usb_dr_mode=host\0"
401 
402 #define CONFIG_KM_NEW_ENV						\
403 	"newenv=sf probe 0;"						\
404 		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
405 		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
406 
407 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
408 #ifndef CONFIG_KM_DEF_ARCH
409 #define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
410 #endif
411 
412 #define CONFIG_EXTRA_ENV_SETTINGS					\
413 	CONFIG_KM_DEF_ENV						\
414 	CONFIG_KM_DEF_ARCH						\
415 	CONFIG_KM_NEW_ENV						\
416 	CONFIG_HW_ENV_SETTINGS						\
417 	"EEprom_ivm=pca9547:70:9\0"					\
418 	""
419 
420 #endif /* _CONFIG_KMP204X_H */
421