1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_PPC_P2041 12 13 #define CONFIG_SYS_TEXT_BASE 0xfff40000 14 15 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 16 17 /* an additionnal option is required for UBI as subpage access is 18 * supported in u-boot */ 19 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 20 21 #define CONFIG_NAND_ECC_BCH 22 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 /* common KM defines */ 26 #include "keymile-common.h" 27 28 #define CONFIG_SYS_RAMBOOT 29 #define CONFIG_RAMBOOT_PBL 30 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 32 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 33 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 34 35 /* High Level Configuration Options */ 36 #define CONFIG_BOOKE 37 #define CONFIG_E500 /* BOOKE e500 family */ 38 #define CONFIG_E500MC /* BOOKE e500mc family */ 39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 40 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 41 #define CONFIG_MP /* support multiple processors */ 42 43 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 44 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 45 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 46 #define CONFIG_PCI /* Enable PCI/PCIE */ 47 #define CONFIG_PCIE1 /* PCIE controller 1 */ 48 #define CONFIG_PCIE3 /* PCIE controller 3 */ 49 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 50 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 51 52 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 53 54 #define CONFIG_FSL_LAW /* Use common FSL init code */ 55 56 /* Environment in SPI Flash */ 57 #define CONFIG_SYS_EXTRA_ENV_RELOC 58 #define CONFIG_ENV_IS_IN_SPI_FLASH 59 #define CONFIG_ENV_SPI_BUS 0 60 #define CONFIG_ENV_SPI_CS 0 61 #define CONFIG_ENV_SPI_MAX_HZ 20000000 62 #define CONFIG_ENV_SPI_MODE 0 63 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 64 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 65 #define CONFIG_ENV_SECT_SIZE 0x010000 66 #define CONFIG_ENV_OFFSET_REDUND 0x110000 67 #define CONFIG_ENV_TOTAL_SIZE 0x020000 68 69 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 70 71 #ifndef __ASSEMBLY__ 72 unsigned long get_board_sys_clk(unsigned long dummy); 73 #endif 74 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 75 76 /* 77 * These can be toggled for performance analysis, otherwise use default. 78 */ 79 #define CONFIG_SYS_CACHE_STASHING 80 #define CONFIG_BACKSIDE_L2_CACHE 81 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 82 #define CONFIG_BTB /* toggle branch predition */ 83 84 #define CONFIG_ENABLE_36BIT_PHYS 85 86 #define CONFIG_ADDR_MAP 87 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 88 89 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 90 91 /* 92 * Config the L3 Cache as L3 SRAM 93 */ 94 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 95 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 96 CONFIG_RAMBOOT_TEXT_BASE) 97 #define CONFIG_SYS_L3_SIZE (1024 << 10) 98 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 99 100 #define CONFIG_SYS_DCSRBAR 0xf0000000 101 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 102 103 /* 104 * DDR Setup 105 */ 106 #define CONFIG_VERY_BIG_RAM 107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 109 110 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 111 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 112 113 #define CONFIG_DDR_SPD 114 #define CONFIG_SYS_FSL_DDR3 115 #define CONFIG_FSL_DDR_INTERACTIVE 116 117 #define CONFIG_SYS_SPD_BUS_NUM 0 118 #define SPD_EEPROM_ADDRESS 0x54 119 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 120 121 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 123 124 /****************************************************************************** 125 * (PRAM usage) 126 * ... ------------------------------------------------------- 127 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 128 * ... |<------------------- pram -------------------------->| 129 * ... ------------------------------------------------------- 130 * @END_OF_RAM: 131 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 132 * @CONFIG_KM_PHRAM: address for /var 133 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 134 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 135 */ 136 137 /* size of rootfs in RAM */ 138 #define CONFIG_KM_ROOTFSSIZE 0x0 139 /* pseudo-non volatile RAM [hex] */ 140 #define CONFIG_KM_PNVRAM 0x80000 141 /* physical RAM MTD size [hex] */ 142 #define CONFIG_KM_PHRAM 0x100000 143 /* reserved pram area at the end of memory [hex] 144 * u-boot reserves some memory for the MP boot page */ 145 #define CONFIG_KM_RESERVED_PRAM 0x1000 146 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 147 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 148 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 149 150 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 151 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 152 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 153 154 /* 155 * Local Bus Definitions 156 */ 157 158 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 159 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 160 161 /* Nand Flash */ 162 #define CONFIG_NAND_FSL_ELBC 163 #define CONFIG_SYS_NAND_BASE 0xffa00000 164 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 165 166 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 167 #define CONFIG_SYS_MAX_NAND_DEVICE 1 168 #define CONFIG_CMD_NAND 169 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 170 171 #define CONFIG_BCH 172 173 /* NAND flash config */ 174 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 175 | BR_PS_8 /* Port Size = 8 bit */ \ 176 | BR_MS_FCM /* MSEL = FCM */ \ 177 | BR_V) /* valid */ 178 179 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 180 | OR_FCM_BCTLD /* LBCTL not ass */ \ 181 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 182 | OR_FCM_RST /* 1 clk read setup */ \ 183 | OR_FCM_PGS /* Large page size */ \ 184 | OR_FCM_CST) /* 0.25 command setup */ 185 186 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 187 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 188 189 /* QRIO FPGA */ 190 #define CONFIG_SYS_QRIO_BASE 0xfb000000 191 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 192 193 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 194 | BR_PS_8 /* Port Size 8 bits */ \ 195 | BR_DECC_OFF /* no error corr */ \ 196 | BR_MS_GPCM /* MSEL = GPCM */ \ 197 | BR_V) /* valid */ 198 199 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 200 | OR_GPCM_BCTLD /* no LCTL assert */ \ 201 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 202 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 203 | OR_GPCM_TRLX /* relaxed tmgs */ \ 204 | OR_GPCM_EAD) /* extra bus clk cycles */ 205 206 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 207 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 208 209 /* bootcounter in QRIO */ 210 #define CONFIG_BOOTCOUNT_LIMIT 211 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 212 213 #define CONFIG_BOARD_EARLY_INIT_F 214 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 215 #define CONFIG_MISC_INIT_F 216 #define CONFIG_MISC_INIT_R 217 #define CONFIG_LAST_STAGE_INIT 218 219 #define CONFIG_HWCONFIG 220 221 /* define to use L1 as initial stack */ 222 #define CONFIG_L1_INIT_RAM 223 #define CONFIG_SYS_INIT_RAM_LOCK 224 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 227 /* The assembler doesn't like typecast */ 228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 229 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 230 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 231 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 232 233 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 234 GENERATED_GBL_DATA_SIZE) 235 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 236 237 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 238 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 239 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 240 241 /* Serial Port - controlled on board with jumper J8 242 * open - index 2 243 * shorted - index 1 244 */ 245 #define CONFIG_CONS_INDEX 1 246 #define CONFIG_SYS_NS16550_SERIAL 247 #define CONFIG_SYS_NS16550_REG_SIZE 1 248 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 249 250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 252 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 253 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 254 255 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 256 257 /* I2C */ 258 259 #define CONFIG_SYS_I2C 260 #define CONFIG_SYS_I2C_INIT_BOARD 261 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 262 #define CONFIG_SYS_NUM_I2C_BUSES 3 263 #define CONFIG_SYS_I2C_MAX_HOPS 1 264 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 265 #define CONFIG_I2C_MULTI_BUS 266 #define CONFIG_I2C_CMD_TREE 267 #define CONFIG_SYS_FSL_I2C_SPEED 400000 268 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 269 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 270 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 271 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 272 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 273 } 274 #ifndef __ASSEMBLY__ 275 void set_sda(int state); 276 void set_scl(int state); 277 int get_sda(void); 278 int get_scl(void); 279 #endif 280 281 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 282 283 /* 284 * eSPI - Enhanced SPI 285 */ 286 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 287 #define CONFIG_SF_DEFAULT_SPEED 20000000 288 #define CONFIG_SF_DEFAULT_MODE 0 289 290 /* 291 * General PCI 292 * Memory space is mapped 1-1, but I/O space must start from 0. 293 */ 294 295 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 296 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 297 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 298 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 299 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 300 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 301 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 302 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 303 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 304 305 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 306 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 307 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 308 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 309 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 310 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 311 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 312 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 313 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 314 315 /* Qman/Bman */ 316 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 317 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 318 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 319 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 320 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 321 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 322 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 323 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 324 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 325 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 326 CONFIG_SYS_BMAN_CENA_SIZE) 327 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 328 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 329 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 330 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 331 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 332 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 333 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 334 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 335 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 336 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 337 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 338 CONFIG_SYS_QMAN_CENA_SIZE) 339 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 340 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 341 342 #define CONFIG_SYS_DPAA_FMAN 343 #define CONFIG_SYS_DPAA_PME 344 /* Default address of microcode for the Linux Fman driver 345 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 346 * ucode is stored after env, so we got 0x120000. 347 */ 348 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 349 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 350 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 351 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 352 353 #define CONFIG_FMAN_ENET 354 #define CONFIG_PHYLIB_10G 355 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 356 357 #define CONFIG_PCI_INDIRECT_BRIDGE 358 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 359 360 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 361 #define CONFIG_DOS_PARTITION 362 363 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 364 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 365 #define CONFIG_SYS_TBIPA_VALUE 8 366 #define CONFIG_PHYLIB /* recommended PHY management */ 367 #define CONFIG_ETHPRIME "FM1@DTSEC5" 368 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 369 370 /* 371 * Environment 372 */ 373 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 374 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 375 376 /* 377 * Hardware Watchdog 378 */ 379 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 380 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 381 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 382 383 384 /* 385 * additionnal command line configuration. 386 */ 387 #define CONFIG_CMD_PCI 388 #define CONFIG_CMD_ERRATA 389 390 /* we don't need flash support */ 391 #define CONFIG_SYS_NO_FLASH 392 #undef CONFIG_FLASH_CFI_MTD 393 #undef CONFIG_JFFS2_CMDLINE 394 395 /* 396 * For booting Linux, the board info and command line data 397 * have to be in the first 64 MB of memory, since this is 398 * the maximum mapped by the Linux kernel during initialization. 399 */ 400 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 401 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 402 403 #ifdef CONFIG_CMD_KGDB 404 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 405 #endif 406 407 #define __USB_PHY_TYPE utmi 408 #define CONFIG_USB_EHCI_FSL 409 410 /* 411 * Environment Configuration 412 */ 413 #define CONFIG_ENV_OVERWRITE 414 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 415 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 416 #endif 417 418 #ifndef MTDIDS_DEFAULT 419 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 420 #endif /* MTDIDS_DEFAULT */ 421 422 #ifndef MTDPARTS_DEFAULT 423 # define MTDPARTS_DEFAULT "mtdparts=" \ 424 "fsl_elbc_nand:" \ 425 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 426 #endif /* MTDPARTS_DEFAULT */ 427 428 /* architecture specific default bootargs */ 429 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 430 431 /* FIXME: FDT_ADDR is unspecified */ 432 #define CONFIG_KM_DEF_ENV_CPU \ 433 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 434 "cramfsloadfdt=" \ 435 "cramfsload ${fdt_addr_r} " \ 436 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 437 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 438 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 439 "update=" \ 440 "sf probe 0;sf erase 0 +${filesize};" \ 441 "sf write ${load_addr_r} 0 ${filesize};\0" \ 442 "set_fdthigh=true\0" \ 443 "checkfdt=true\0" \ 444 "" 445 446 #define CONFIG_HW_ENV_SETTINGS \ 447 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 448 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 449 "usb_dr_mode=host\0" 450 451 #define CONFIG_KM_NEW_ENV \ 452 "newenv=sf probe 0;" \ 453 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 454 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 455 456 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 457 #ifndef CONFIG_KM_DEF_ARCH 458 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 459 #endif 460 461 #define CONFIG_EXTRA_ENV_SETTINGS \ 462 CONFIG_KM_DEF_ENV \ 463 CONFIG_KM_DEF_ARCH \ 464 CONFIG_KM_NEW_ENV \ 465 CONFIG_HW_ENV_SETTINGS \ 466 "EEprom_ivm=pca9547:70:9\0" \ 467 "" 468 469 #endif /* _CONFIG_KMP204X_H */ 470