1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2013 Keymile AG 4 * Valentin Longchamp <valentin.longchamp@keymile.com> 5 */ 6 7 #ifndef _CONFIG_KMP204X_H 8 #define _CONFIG_KMP204X_H 9 10 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 11 12 /* an additionnal option is required for UBI as subpage access is 13 * supported in u-boot */ 14 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 15 16 #define CONFIG_NAND_ECC_BCH 17 18 /* common KM defines */ 19 #include "keymile-common.h" 20 21 #define CONFIG_SYS_RAMBOOT 22 #define CONFIG_RAMBOOT_PBL 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 26 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 27 28 /* High Level Configuration Options */ 29 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 30 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 31 32 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 33 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 34 #define CONFIG_PCIE1 /* PCIE controller 1 */ 35 #define CONFIG_PCIE3 /* PCIE controller 3 */ 36 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 37 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 38 39 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 40 41 /* Environment in SPI Flash */ 42 #define CONFIG_SYS_EXTRA_ENV_RELOC 43 #define CONFIG_ENV_SPI_BUS 0 44 #define CONFIG_ENV_SPI_CS 0 45 #define CONFIG_ENV_SPI_MAX_HZ 20000000 46 #define CONFIG_ENV_SPI_MODE 0 47 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 48 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 49 #define CONFIG_ENV_SECT_SIZE 0x010000 50 #define CONFIG_ENV_OFFSET_REDUND 0x110000 51 #define CONFIG_ENV_TOTAL_SIZE 0x020000 52 53 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 54 55 #ifndef __ASSEMBLY__ 56 unsigned long get_board_sys_clk(unsigned long dummy); 57 #endif 58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_SYS_CACHE_STASHING 64 #define CONFIG_BACKSIDE_L2_CACHE 65 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 66 #define CONFIG_BTB /* toggle branch predition */ 67 68 #define CONFIG_ENABLE_36BIT_PHYS 69 70 #define CONFIG_ADDR_MAP 71 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 72 73 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 74 75 /* 76 * Config the L3 Cache as L3 SRAM 77 */ 78 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 79 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 80 CONFIG_RAMBOOT_TEXT_BASE) 81 #define CONFIG_SYS_L3_SIZE (1024 << 10) 82 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 83 84 #define CONFIG_SYS_DCSRBAR 0xf0000000 85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 86 87 /* 88 * DDR Setup 89 */ 90 #define CONFIG_VERY_BIG_RAM 91 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 93 94 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 95 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 96 97 #define CONFIG_DDR_SPD 98 #define CONFIG_FSL_DDR_INTERACTIVE 99 100 #define CONFIG_SYS_SPD_BUS_NUM 0 101 #define SPD_EEPROM_ADDRESS 0x54 102 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 103 104 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 105 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 106 107 /****************************************************************************** 108 * (PRAM usage) 109 * ... ------------------------------------------------------- 110 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 111 * ... |<------------------- pram -------------------------->| 112 * ... ------------------------------------------------------- 113 * @END_OF_RAM: 114 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 115 * @CONFIG_KM_PHRAM: address for /var 116 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 117 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 118 */ 119 120 /* size of rootfs in RAM */ 121 #define CONFIG_KM_ROOTFSSIZE 0x0 122 /* pseudo-non volatile RAM [hex] */ 123 #define CONFIG_KM_PNVRAM 0x80000 124 /* physical RAM MTD size [hex] */ 125 #define CONFIG_KM_PHRAM 0x100000 126 /* reserved pram area at the end of memory [hex] 127 * u-boot reserves some memory for the MP boot page */ 128 #define CONFIG_KM_RESERVED_PRAM 0x1000 129 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 130 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 131 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 132 133 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 134 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 135 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 136 137 /* 138 * Local Bus Definitions 139 */ 140 141 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 142 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 143 144 /* Nand Flash */ 145 #define CONFIG_NAND_FSL_ELBC 146 #define CONFIG_SYS_NAND_BASE 0xffa00000 147 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 148 149 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 150 #define CONFIG_SYS_MAX_NAND_DEVICE 1 151 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 152 153 /* NAND flash config */ 154 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 155 | BR_PS_8 /* Port Size = 8 bit */ \ 156 | BR_MS_FCM /* MSEL = FCM */ \ 157 | BR_V) /* valid */ 158 159 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 160 | OR_FCM_BCTLD /* LBCTL not ass */ \ 161 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 162 | OR_FCM_RST /* 1 clk read setup */ \ 163 | OR_FCM_PGS /* Large page size */ \ 164 | OR_FCM_CST) /* 0.25 command setup */ 165 166 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 167 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 168 169 /* QRIO FPGA */ 170 #define CONFIG_SYS_QRIO_BASE 0xfb000000 171 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 172 173 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 174 | BR_PS_8 /* Port Size 8 bits */ \ 175 | BR_DECC_OFF /* no error corr */ \ 176 | BR_MS_GPCM /* MSEL = GPCM */ \ 177 | BR_V) /* valid */ 178 179 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 180 | OR_GPCM_BCTLD /* no LCTL assert */ \ 181 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 182 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 183 | OR_GPCM_TRLX /* relaxed tmgs */ \ 184 | OR_GPCM_EAD) /* extra bus clk cycles */ 185 186 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 187 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 188 189 #define CONFIG_MISC_INIT_F 190 191 #define CONFIG_HWCONFIG 192 193 /* define to use L1 as initial stack */ 194 #define CONFIG_L1_INIT_RAM 195 #define CONFIG_SYS_INIT_RAM_LOCK 196 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 199 /* The assembler doesn't like typecast */ 200 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 201 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 202 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 203 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 204 205 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 206 GENERATED_GBL_DATA_SIZE) 207 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 208 209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 210 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 211 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 212 213 /* Serial Port - controlled on board with jumper J8 214 * open - index 2 215 * shorted - index 1 216 */ 217 #define CONFIG_SYS_NS16550_SERIAL 218 #define CONFIG_SYS_NS16550_REG_SIZE 1 219 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 220 221 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 222 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 223 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 224 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 225 226 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 227 228 /* I2C */ 229 230 #define CONFIG_SYS_I2C 231 #define CONFIG_SYS_I2C_INIT_BOARD 232 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 233 #define CONFIG_SYS_NUM_I2C_BUSES 3 234 #define CONFIG_SYS_I2C_MAX_HOPS 1 235 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 236 #define CONFIG_I2C_MULTI_BUS 237 #define CONFIG_I2C_CMD_TREE 238 #define CONFIG_SYS_FSL_I2C_SPEED 400000 239 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 240 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 241 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 242 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 243 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 244 } 245 #ifndef __ASSEMBLY__ 246 void set_sda(int state); 247 void set_scl(int state); 248 int get_sda(void); 249 int get_scl(void); 250 #endif 251 252 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 253 254 /* 255 * eSPI - Enhanced SPI 256 */ 257 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 258 #define CONFIG_SF_DEFAULT_SPEED 20000000 259 #define CONFIG_SF_DEFAULT_MODE 0 260 261 /* 262 * General PCI 263 * Memory space is mapped 1-1, but I/O space must start from 0. 264 */ 265 266 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 267 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 268 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 269 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 270 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 271 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 272 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 273 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 274 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 275 276 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 277 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 278 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 279 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 280 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 281 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 282 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 283 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 284 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 285 286 /* Qman/Bman */ 287 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 288 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 289 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 290 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 291 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 292 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 293 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 294 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 295 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 296 CONFIG_SYS_BMAN_CENA_SIZE) 297 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 298 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 299 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 300 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 301 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 302 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 303 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 304 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 305 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 306 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 307 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 308 CONFIG_SYS_QMAN_CENA_SIZE) 309 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 310 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 311 312 #define CONFIG_SYS_DPAA_FMAN 313 #define CONFIG_SYS_DPAA_PME 314 /* Default address of microcode for the Linux Fman driver 315 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 316 * ucode is stored after env, so we got 0x120000. 317 */ 318 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 319 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 320 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 321 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 322 323 #define CONFIG_FMAN_ENET 324 #define CONFIG_PHYLIB_10G 325 326 #define CONFIG_PCI_INDIRECT_BRIDGE 327 328 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 329 330 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 331 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 332 #define CONFIG_SYS_TBIPA_VALUE 8 333 #define CONFIG_ETHPRIME "FM1@DTSEC5" 334 335 /* 336 * Environment 337 */ 338 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 339 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 340 341 /* 342 * Hardware Watchdog 343 */ 344 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 345 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 346 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 347 348 349 /* 350 * additionnal command line configuration. 351 */ 352 353 /* we don't need flash support */ 354 #undef CONFIG_FLASH_CFI_MTD 355 #undef CONFIG_JFFS2_CMDLINE 356 357 /* 358 * For booting Linux, the board info and command line data 359 * have to be in the first 64 MB of memory, since this is 360 * the maximum mapped by the Linux kernel during initialization. 361 */ 362 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 363 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 364 365 #ifdef CONFIG_CMD_KGDB 366 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 367 #endif 368 369 #define __USB_PHY_TYPE utmi 370 #define CONFIG_USB_EHCI_FSL 371 372 /* 373 * Environment Configuration 374 */ 375 #define CONFIG_ENV_OVERWRITE 376 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 377 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 378 #endif 379 380 /* architecture specific default bootargs */ 381 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 382 383 /* FIXME: FDT_ADDR is unspecified */ 384 #define CONFIG_KM_DEF_ENV_CPU \ 385 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 386 "cramfsloadfdt=" \ 387 "cramfsload ${fdt_addr_r} " \ 388 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 389 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 390 "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0" \ 391 "update=" \ 392 "sf probe 0;sf erase 0 +${filesize};" \ 393 "sf write ${load_addr_r} 0 ${filesize};\0" \ 394 "set_fdthigh=true\0" \ 395 "checkfdt=true\0" \ 396 "" 397 398 #define CONFIG_HW_ENV_SETTINGS \ 399 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 400 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 401 "usb_dr_mode=host\0" 402 403 #define CONFIG_KM_NEW_ENV \ 404 "newenv=sf probe 0;" \ 405 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 406 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 407 408 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 409 #ifndef CONFIG_KM_DEF_ARCH 410 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 411 #endif 412 413 #define CONFIG_EXTRA_ENV_SETTINGS \ 414 CONFIG_KM_DEF_ENV \ 415 CONFIG_KM_DEF_ARCH \ 416 CONFIG_KM_NEW_ENV \ 417 CONFIG_HW_ENV_SETTINGS \ 418 "EEprom_ivm=pca9547:70:9\0" \ 419 "" 420 421 #endif /* _CONFIG_KMP204X_H */ 422