1 /*
2  * (C) Copyright 2013 Keymile AG
3  * Valentin Longchamp <valentin.longchamp@keymile.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _CONFIG_KMP204X_H
9 #define _CONFIG_KMP204X_H
10 
11 #define CONFIG_SYS_TEXT_BASE	0xfff40000
12 
13 #define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
14 
15 /* an additionnal option is required for UBI as subpage access is
16  * supported in u-boot */
17 #define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
18 
19 #define CONFIG_NAND_ECC_BCH
20 
21 /* common KM defines */
22 #include "keymile-common.h"
23 
24 #define CONFIG_SYS_RAMBOOT
25 #define CONFIG_RAMBOOT_PBL
26 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
28 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
29 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
30 
31 /* High Level Configuration Options */
32 #define CONFIG_BOOKE
33 #define CONFIG_E500			/* BOOKE e500 family */
34 #define CONFIG_E500MC			/* BOOKE e500mc family */
35 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
36 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
37 #define CONFIG_MP			/* support multiple processors */
38 
39 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
40 #define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
41 #define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
42 #define CONFIG_PCIE1			/* PCIE controller 1 */
43 #define CONFIG_PCIE3			/* PCIE controller 3 */
44 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
45 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
46 
47 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
48 
49 /* Environment in SPI Flash */
50 #define CONFIG_SYS_EXTRA_ENV_RELOC
51 #define CONFIG_ENV_IS_IN_SPI_FLASH
52 #define CONFIG_ENV_SPI_BUS              0
53 #define CONFIG_ENV_SPI_CS               0
54 #define CONFIG_ENV_SPI_MAX_HZ           20000000
55 #define CONFIG_ENV_SPI_MODE             0
56 #define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
57 #define CONFIG_ENV_SIZE			0x004000	/* 16K env */
58 #define CONFIG_ENV_SECT_SIZE            0x010000
59 #define CONFIG_ENV_OFFSET_REDUND	0x110000
60 #define CONFIG_ENV_TOTAL_SIZE		0x020000
61 
62 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
63 
64 #ifndef __ASSEMBLY__
65 unsigned long get_board_sys_clk(unsigned long dummy);
66 #endif
67 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
68 
69 /*
70  * These can be toggled for performance analysis, otherwise use default.
71  */
72 #define CONFIG_SYS_CACHE_STASHING
73 #define CONFIG_BACKSIDE_L2_CACHE
74 #define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
75 #define CONFIG_BTB			/* toggle branch predition */
76 
77 #define CONFIG_ENABLE_36BIT_PHYS
78 
79 #define CONFIG_ADDR_MAP
80 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
81 
82 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS	/* POST memory regions test */
83 
84 /*
85  *  Config the L3 Cache as L3 SRAM
86  */
87 #define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
88 #define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
89 		CONFIG_RAMBOOT_TEXT_BASE)
90 #define CONFIG_SYS_L3_SIZE		(1024 << 10)
91 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
92 
93 #define CONFIG_SYS_DCSRBAR		0xf0000000
94 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
95 
96 /*
97  * DDR Setup
98  */
99 #define CONFIG_VERY_BIG_RAM
100 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
101 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
102 
103 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
104 #define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
105 
106 #define CONFIG_DDR_SPD
107 #define CONFIG_SYS_FSL_DDR3
108 #define CONFIG_FSL_DDR_INTERACTIVE
109 
110 #define CONFIG_SYS_SPD_BUS_NUM	0
111 #define SPD_EEPROM_ADDRESS	0x54
112 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
113 
114 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
115 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
116 
117 /******************************************************************************
118  * (PRAM usage)
119  * ... -------------------------------------------------------
120  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
121  * ... |<------------------- pram -------------------------->|
122  * ... -------------------------------------------------------
123  * @END_OF_RAM:
124  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
125  * @CONFIG_KM_PHRAM: address for /var
126  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
127  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
128  */
129 
130 /* size of rootfs in RAM */
131 #define CONFIG_KM_ROOTFSSIZE	0x0
132 /* pseudo-non volatile RAM [hex] */
133 #define CONFIG_KM_PNVRAM	0x80000
134 /* physical RAM MTD size [hex] */
135 #define CONFIG_KM_PHRAM		0x100000
136 /* reserved pram area at the end of memory [hex]
137  * u-boot reserves some memory for the MP boot page */
138 #define CONFIG_KM_RESERVED_PRAM	0x1000
139 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
140  * is not valid yet, which is the case for when u-boot copies itself to RAM */
141 #define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
142 
143 #define CONFIG_KM_CRAMFS_ADDR	0x2000000
144 #define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
145 #define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
146 
147 /*
148  * Local Bus Definitions
149  */
150 
151 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
152 #define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
153 
154 /* Nand Flash */
155 #define CONFIG_NAND_FSL_ELBC
156 #define CONFIG_SYS_NAND_BASE		0xffa00000
157 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
158 
159 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
160 #define CONFIG_SYS_MAX_NAND_DEVICE	1
161 #define CONFIG_CMD_NAND
162 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
163 
164 #define CONFIG_BCH
165 
166 /* NAND flash config */
167 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
168 			       | BR_PS_8	       /* Port Size = 8 bit */ \
169 			       | BR_MS_FCM	       /* MSEL = FCM */ \
170 			       | BR_V)		       /* valid */
171 
172 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
173 			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
174 			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
175 			       | OR_FCM_RST	/* 1 clk read setup */	\
176 			       | OR_FCM_PGS	/* Large page size */	\
177 			       | OR_FCM_CST)	/* 0.25 command setup */
178 
179 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
180 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
181 
182 /* QRIO FPGA */
183 #define CONFIG_SYS_QRIO_BASE		0xfb000000
184 #define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
185 
186 #define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
187 				| BR_PS_8	/* Port Size 8 bits */ \
188 				| BR_DECC_OFF	/* no error corr */ \
189 				| BR_MS_GPCM	/* MSEL = GPCM */ \
190 				| BR_V)		/* valid */
191 
192 #define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
193 				| OR_GPCM_BCTLD /* no LCTL assert */ \
194 				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
195 				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
196 				| OR_GPCM_TRLX /* relaxed tmgs */ \
197 				| OR_GPCM_EAD) /* extra bus clk cycles */
198 
199 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
200 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
201 
202 /* bootcounter in QRIO */
203 #define CONFIG_BOOTCOUNT_LIMIT
204 #define CONFIG_SYS_BOOTCOUNT_ADDR	(CONFIG_SYS_QRIO_BASE + 0x20)
205 
206 #define CONFIG_BOARD_EARLY_INIT_F
207 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
208 #define CONFIG_MISC_INIT_F
209 #define CONFIG_MISC_INIT_R
210 #define CONFIG_LAST_STAGE_INIT
211 
212 #define CONFIG_HWCONFIG
213 
214 /* define to use L1 as initial stack */
215 #define CONFIG_L1_INIT_RAM
216 #define CONFIG_SYS_INIT_RAM_LOCK
217 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
218 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
219 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
220 /* The assembler doesn't like typecast */
221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
222 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
223 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
224 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
225 
226 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
227 					GENERATED_GBL_DATA_SIZE)
228 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
229 
230 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
231 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
232 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
233 
234 /* Serial Port - controlled on board with jumper J8
235  * open - index 2
236  * shorted - index 1
237  */
238 #define CONFIG_CONS_INDEX	1
239 #define CONFIG_SYS_NS16550_SERIAL
240 #define CONFIG_SYS_NS16550_REG_SIZE	1
241 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
242 
243 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
244 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
245 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
246 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
247 
248 #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
249 
250 /* I2C */
251 
252 #define CONFIG_SYS_I2C
253 #define CONFIG_SYS_I2C_INIT_BOARD
254 #define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
255 #define CONFIG_SYS_NUM_I2C_BUSES	3
256 #define CONFIG_SYS_I2C_MAX_HOPS		1
257 #define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
258 #define CONFIG_I2C_MULTI_BUS
259 #define CONFIG_I2C_CMD_TREE
260 #define CONFIG_SYS_FSL_I2C_SPEED	400000
261 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
262 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
263 #define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
264 					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
265 					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
266 				}
267 #ifndef __ASSEMBLY__
268 void set_sda(int state);
269 void set_scl(int state);
270 int get_sda(void);
271 int get_scl(void);
272 #endif
273 
274 #define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
275 
276 /*
277  * eSPI - Enhanced SPI
278  */
279 #define CONFIG_SPI_FLASH_BAR	/* 4 byte-addressing */
280 #define CONFIG_SF_DEFAULT_SPEED         20000000
281 #define CONFIG_SF_DEFAULT_MODE          0
282 
283 /*
284  * General PCI
285  * Memory space is mapped 1-1, but I/O space must start from 0.
286  */
287 
288 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
289 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
290 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
291 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
292 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
293 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
294 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
295 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
296 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
297 
298 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
299 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
300 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
301 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
302 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
303 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
304 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
305 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
306 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
307 
308 /* Qman/Bman */
309 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
310 #define CONFIG_SYS_BMAN_NUM_PORTALS	10
311 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
312 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
313 #define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
314 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
315 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
316 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
317 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
318 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
319 					CONFIG_SYS_BMAN_CENA_SIZE)
320 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
321 #define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
322 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
323 #define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
324 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
325 #define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
326 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
327 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
328 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
329 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
330 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
331 					CONFIG_SYS_QMAN_CENA_SIZE)
332 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
333 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
334 
335 #define CONFIG_SYS_DPAA_FMAN
336 #define CONFIG_SYS_DPAA_PME
337 /* Default address of microcode for the Linux Fman driver
338  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
339  * ucode is stored after env, so we got 0x120000.
340  */
341 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
342 #define CONFIG_SYS_FMAN_FW_ADDR	0x120000
343 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
344 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
345 
346 #define CONFIG_FMAN_ENET
347 #define CONFIG_PHYLIB_10G
348 #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
349 
350 #define CONFIG_PCI_INDIRECT_BRIDGE
351 
352 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
353 #define CONFIG_DOS_PARTITION
354 
355 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
356 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
357 #define CONFIG_SYS_TBIPA_VALUE	8
358 #define CONFIG_PHYLIB		/* recommended PHY management */
359 #define CONFIG_ETHPRIME		"FM1@DTSEC5"
360 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
361 
362 /*
363  * Environment
364  */
365 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
366 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
367 
368 /*
369  * Hardware Watchdog
370  */
371 #define CONFIG_WATCHDOG			/* enable CPU watchdog */
372 #define CONFIG_WATCHDOG_PRESC 34	/* wdog prescaler 2^(64-34) (~10min) */
373 #define CONFIG_WATCHDOG_RC WRC_CHIP	/* reset chip on watchdog event */
374 
375 
376 /*
377  * additionnal command line configuration.
378  */
379 #define CONFIG_CMD_PCI
380 #define CONFIG_CMD_ERRATA
381 
382 /* we don't need flash support */
383 #define CONFIG_SYS_NO_FLASH
384 #undef CONFIG_FLASH_CFI_MTD
385 #undef CONFIG_JFFS2_CMDLINE
386 
387 /*
388  * For booting Linux, the board info and command line data
389  * have to be in the first 64 MB of memory, since this is
390  * the maximum mapped by the Linux kernel during initialization.
391  */
392 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
393 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
394 
395 #ifdef CONFIG_CMD_KGDB
396 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
397 #endif
398 
399 #define __USB_PHY_TYPE	utmi
400 #define CONFIG_USB_EHCI_FSL
401 
402 /*
403  * Environment Configuration
404  */
405 #define CONFIG_ENV_OVERWRITE
406 #ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
407 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
408 #endif
409 
410 #ifndef MTDIDS_DEFAULT
411 # define MTDIDS_DEFAULT		"nand0=fsl_elbc_nand"
412 #endif /* MTDIDS_DEFAULT */
413 
414 #ifndef MTDPARTS_DEFAULT
415 # define MTDPARTS_DEFAULT	"mtdparts="			\
416 	"fsl_elbc_nand:"						\
417 		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
418 #endif /* MTDPARTS_DEFAULT */
419 
420 /* architecture specific default bootargs */
421 #define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
422 
423 /* FIXME: FDT_ADDR is unspecified */
424 #define CONFIG_KM_DEF_ENV_CPU						\
425 	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
426 	"cramfsloadfdt="						\
427 		"cramfsload ${fdt_addr_r} "				\
428 		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
429 	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
430 	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0"		\
431 	"update="							\
432 		"sf probe 0;sf erase 0 +${filesize};"			\
433 		"sf write ${load_addr_r} 0 ${filesize};\0"		\
434 	"set_fdthigh=true\0"						\
435 	"checkfdt=true\0"						\
436 	""
437 
438 #define CONFIG_HW_ENV_SETTINGS						\
439 	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
440 	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
441 	"usb_dr_mode=host\0"
442 
443 #define CONFIG_KM_NEW_ENV						\
444 	"newenv=sf probe 0;"						\
445 		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
446 		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
447 
448 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
449 #ifndef CONFIG_KM_DEF_ARCH
450 #define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
451 #endif
452 
453 #define CONFIG_EXTRA_ENV_SETTINGS					\
454 	CONFIG_KM_DEF_ENV						\
455 	CONFIG_KM_DEF_ARCH						\
456 	CONFIG_KM_NEW_ENV						\
457 	CONFIG_HW_ENV_SETTINGS						\
458 	"EEprom_ivm=pca9547:70:9\0"					\
459 	""
460 
461 #endif /* _CONFIG_KMP204X_H */
462