1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_PPC_P2041 12 13 #define CONFIG_SYS_TEXT_BASE 0xfff40000 14 15 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 16 17 /* an additionnal option is required for UBI as subpage access is 18 * supported in u-boot */ 19 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 20 21 #define CONFIG_NAND_ECC_BCH 22 23 /* common KM defines */ 24 #include "keymile-common.h" 25 26 #define CONFIG_SYS_RAMBOOT 27 #define CONFIG_RAMBOOT_PBL 28 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 30 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 31 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 32 33 /* High Level Configuration Options */ 34 #define CONFIG_BOOKE 35 #define CONFIG_E500 /* BOOKE e500 family */ 36 #define CONFIG_E500MC /* BOOKE e500mc family */ 37 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 38 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 44 #define CONFIG_PCIE1 /* PCIE controller 1 */ 45 #define CONFIG_PCIE3 /* PCIE controller 3 */ 46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 48 49 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 50 51 #define CONFIG_FSL_LAW /* Use common FSL init code */ 52 53 /* Environment in SPI Flash */ 54 #define CONFIG_SYS_EXTRA_ENV_RELOC 55 #define CONFIG_ENV_IS_IN_SPI_FLASH 56 #define CONFIG_ENV_SPI_BUS 0 57 #define CONFIG_ENV_SPI_CS 0 58 #define CONFIG_ENV_SPI_MAX_HZ 20000000 59 #define CONFIG_ENV_SPI_MODE 0 60 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 61 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 62 #define CONFIG_ENV_SECT_SIZE 0x010000 63 #define CONFIG_ENV_OFFSET_REDUND 0x110000 64 #define CONFIG_ENV_TOTAL_SIZE 0x020000 65 66 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 67 68 #ifndef __ASSEMBLY__ 69 unsigned long get_board_sys_clk(unsigned long dummy); 70 #endif 71 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 72 73 /* 74 * These can be toggled for performance analysis, otherwise use default. 75 */ 76 #define CONFIG_SYS_CACHE_STASHING 77 #define CONFIG_BACKSIDE_L2_CACHE 78 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 79 #define CONFIG_BTB /* toggle branch predition */ 80 81 #define CONFIG_ENABLE_36BIT_PHYS 82 83 #define CONFIG_ADDR_MAP 84 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 85 86 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 87 88 /* 89 * Config the L3 Cache as L3 SRAM 90 */ 91 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 92 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 93 CONFIG_RAMBOOT_TEXT_BASE) 94 #define CONFIG_SYS_L3_SIZE (1024 << 10) 95 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 96 97 #define CONFIG_SYS_DCSRBAR 0xf0000000 98 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 99 100 /* 101 * DDR Setup 102 */ 103 #define CONFIG_VERY_BIG_RAM 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 109 110 #define CONFIG_DDR_SPD 111 #define CONFIG_SYS_FSL_DDR3 112 #define CONFIG_FSL_DDR_INTERACTIVE 113 114 #define CONFIG_SYS_SPD_BUS_NUM 0 115 #define SPD_EEPROM_ADDRESS 0x54 116 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 117 118 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 119 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 120 121 /****************************************************************************** 122 * (PRAM usage) 123 * ... ------------------------------------------------------- 124 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 125 * ... |<------------------- pram -------------------------->| 126 * ... ------------------------------------------------------- 127 * @END_OF_RAM: 128 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 129 * @CONFIG_KM_PHRAM: address for /var 130 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 131 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 132 */ 133 134 /* size of rootfs in RAM */ 135 #define CONFIG_KM_ROOTFSSIZE 0x0 136 /* pseudo-non volatile RAM [hex] */ 137 #define CONFIG_KM_PNVRAM 0x80000 138 /* physical RAM MTD size [hex] */ 139 #define CONFIG_KM_PHRAM 0x100000 140 /* reserved pram area at the end of memory [hex] 141 * u-boot reserves some memory for the MP boot page */ 142 #define CONFIG_KM_RESERVED_PRAM 0x1000 143 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 144 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 145 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 146 147 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 148 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 149 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 150 151 /* 152 * Local Bus Definitions 153 */ 154 155 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 156 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 157 158 /* Nand Flash */ 159 #define CONFIG_NAND_FSL_ELBC 160 #define CONFIG_SYS_NAND_BASE 0xffa00000 161 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 162 163 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 164 #define CONFIG_SYS_MAX_NAND_DEVICE 1 165 #define CONFIG_CMD_NAND 166 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 167 168 #define CONFIG_BCH 169 170 /* NAND flash config */ 171 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 172 | BR_PS_8 /* Port Size = 8 bit */ \ 173 | BR_MS_FCM /* MSEL = FCM */ \ 174 | BR_V) /* valid */ 175 176 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 177 | OR_FCM_BCTLD /* LBCTL not ass */ \ 178 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 179 | OR_FCM_RST /* 1 clk read setup */ \ 180 | OR_FCM_PGS /* Large page size */ \ 181 | OR_FCM_CST) /* 0.25 command setup */ 182 183 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 184 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 185 186 /* QRIO FPGA */ 187 #define CONFIG_SYS_QRIO_BASE 0xfb000000 188 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 189 190 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 191 | BR_PS_8 /* Port Size 8 bits */ \ 192 | BR_DECC_OFF /* no error corr */ \ 193 | BR_MS_GPCM /* MSEL = GPCM */ \ 194 | BR_V) /* valid */ 195 196 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 197 | OR_GPCM_BCTLD /* no LCTL assert */ \ 198 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 199 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 200 | OR_GPCM_TRLX /* relaxed tmgs */ \ 201 | OR_GPCM_EAD) /* extra bus clk cycles */ 202 203 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 204 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 205 206 /* bootcounter in QRIO */ 207 #define CONFIG_BOOTCOUNT_LIMIT 208 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 209 210 #define CONFIG_BOARD_EARLY_INIT_F 211 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 212 #define CONFIG_MISC_INIT_F 213 #define CONFIG_MISC_INIT_R 214 #define CONFIG_LAST_STAGE_INIT 215 216 #define CONFIG_HWCONFIG 217 218 /* define to use L1 as initial stack */ 219 #define CONFIG_L1_INIT_RAM 220 #define CONFIG_SYS_INIT_RAM_LOCK 221 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 222 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 224 /* The assembler doesn't like typecast */ 225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 226 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 227 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 228 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 229 230 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 231 GENERATED_GBL_DATA_SIZE) 232 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 233 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 235 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 236 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 237 238 /* Serial Port - controlled on board with jumper J8 239 * open - index 2 240 * shorted - index 1 241 */ 242 #define CONFIG_CONS_INDEX 1 243 #define CONFIG_SYS_NS16550_SERIAL 244 #define CONFIG_SYS_NS16550_REG_SIZE 1 245 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 246 247 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 248 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 249 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 250 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 251 252 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 253 254 /* I2C */ 255 256 #define CONFIG_SYS_I2C 257 #define CONFIG_SYS_I2C_INIT_BOARD 258 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 259 #define CONFIG_SYS_NUM_I2C_BUSES 3 260 #define CONFIG_SYS_I2C_MAX_HOPS 1 261 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 262 #define CONFIG_I2C_MULTI_BUS 263 #define CONFIG_I2C_CMD_TREE 264 #define CONFIG_SYS_FSL_I2C_SPEED 400000 265 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 266 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 267 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 268 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 269 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 270 } 271 #ifndef __ASSEMBLY__ 272 void set_sda(int state); 273 void set_scl(int state); 274 int get_sda(void); 275 int get_scl(void); 276 #endif 277 278 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 279 280 /* 281 * eSPI - Enhanced SPI 282 */ 283 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 284 #define CONFIG_SF_DEFAULT_SPEED 20000000 285 #define CONFIG_SF_DEFAULT_MODE 0 286 287 /* 288 * General PCI 289 * Memory space is mapped 1-1, but I/O space must start from 0. 290 */ 291 292 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 293 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 294 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 295 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 296 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 297 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 298 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 299 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 300 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 301 302 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 303 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 304 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 305 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 306 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 307 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 308 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 309 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 310 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 311 312 /* Qman/Bman */ 313 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 314 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 315 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 316 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 317 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 318 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 319 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 320 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 321 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 322 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 323 CONFIG_SYS_BMAN_CENA_SIZE) 324 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 325 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 326 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 327 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 328 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 329 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 330 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 331 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 332 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 333 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 334 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 335 CONFIG_SYS_QMAN_CENA_SIZE) 336 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 337 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 338 339 #define CONFIG_SYS_DPAA_FMAN 340 #define CONFIG_SYS_DPAA_PME 341 /* Default address of microcode for the Linux Fman driver 342 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 343 * ucode is stored after env, so we got 0x120000. 344 */ 345 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 346 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 347 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 348 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 349 350 #define CONFIG_FMAN_ENET 351 #define CONFIG_PHYLIB_10G 352 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 353 354 #define CONFIG_PCI_INDIRECT_BRIDGE 355 356 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 357 #define CONFIG_DOS_PARTITION 358 359 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 360 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 361 #define CONFIG_SYS_TBIPA_VALUE 8 362 #define CONFIG_PHYLIB /* recommended PHY management */ 363 #define CONFIG_ETHPRIME "FM1@DTSEC5" 364 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 365 366 /* 367 * Environment 368 */ 369 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 370 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 371 372 /* 373 * Hardware Watchdog 374 */ 375 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 376 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 377 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 378 379 380 /* 381 * additionnal command line configuration. 382 */ 383 #define CONFIG_CMD_PCI 384 #define CONFIG_CMD_ERRATA 385 386 /* we don't need flash support */ 387 #define CONFIG_SYS_NO_FLASH 388 #undef CONFIG_FLASH_CFI_MTD 389 #undef CONFIG_JFFS2_CMDLINE 390 391 /* 392 * For booting Linux, the board info and command line data 393 * have to be in the first 64 MB of memory, since this is 394 * the maximum mapped by the Linux kernel during initialization. 395 */ 396 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 397 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 398 399 #ifdef CONFIG_CMD_KGDB 400 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 401 #endif 402 403 #define __USB_PHY_TYPE utmi 404 #define CONFIG_USB_EHCI_FSL 405 406 /* 407 * Environment Configuration 408 */ 409 #define CONFIG_ENV_OVERWRITE 410 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 411 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 412 #endif 413 414 #ifndef MTDIDS_DEFAULT 415 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 416 #endif /* MTDIDS_DEFAULT */ 417 418 #ifndef MTDPARTS_DEFAULT 419 # define MTDPARTS_DEFAULT "mtdparts=" \ 420 "fsl_elbc_nand:" \ 421 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 422 #endif /* MTDPARTS_DEFAULT */ 423 424 /* architecture specific default bootargs */ 425 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 426 427 /* FIXME: FDT_ADDR is unspecified */ 428 #define CONFIG_KM_DEF_ENV_CPU \ 429 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 430 "cramfsloadfdt=" \ 431 "cramfsload ${fdt_addr_r} " \ 432 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 433 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 434 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 435 "update=" \ 436 "sf probe 0;sf erase 0 +${filesize};" \ 437 "sf write ${load_addr_r} 0 ${filesize};\0" \ 438 "set_fdthigh=true\0" \ 439 "checkfdt=true\0" \ 440 "" 441 442 #define CONFIG_HW_ENV_SETTINGS \ 443 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 444 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 445 "usb_dr_mode=host\0" 446 447 #define CONFIG_KM_NEW_ENV \ 448 "newenv=sf probe 0;" \ 449 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 450 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 451 452 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 453 #ifndef CONFIG_KM_DEF_ARCH 454 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 455 #endif 456 457 #define CONFIG_EXTRA_ENV_SETTINGS \ 458 CONFIG_KM_DEF_ENV \ 459 CONFIG_KM_DEF_ARCH \ 460 CONFIG_KM_NEW_ENV \ 461 CONFIG_HW_ENV_SETTINGS \ 462 "EEprom_ivm=pca9547:70:9\0" \ 463 "" 464 465 #endif /* _CONFIG_KMP204X_H */ 466