1 /* 2 * (C) Copyright 2013 Keymile AG 3 * Valentin Longchamp <valentin.longchamp@keymile.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _CONFIG_KMP204X_H 9 #define _CONFIG_KMP204X_H 10 11 #define CONFIG_PPC_P2041 12 13 #define CONFIG_SYS_TEXT_BASE 0xfff40000 14 15 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" 16 17 /* an additionnal option is required for UBI as subpage access is 18 * supported in u-boot */ 19 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 20 21 #define CONFIG_NAND_ECC_BCH 22 23 /* common KM defines */ 24 #include "keymile-common.h" 25 26 #define CONFIG_SYS_RAMBOOT 27 #define CONFIG_RAMBOOT_PBL 28 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 29 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 30 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg 31 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg 32 33 /* High Level Configuration Options */ 34 #define CONFIG_BOOKE 35 #define CONFIG_E500 /* BOOKE e500 family */ 36 #define CONFIG_E500MC /* BOOKE e500mc family */ 37 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 38 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 44 #define CONFIG_PCI /* Enable PCI/PCIE */ 45 #define CONFIG_PCIE1 /* PCIE controller 1 */ 46 #define CONFIG_PCIE3 /* PCIE controller 3 */ 47 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 50 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 51 52 #define CONFIG_FSL_LAW /* Use common FSL init code */ 53 54 /* Environment in SPI Flash */ 55 #define CONFIG_SYS_EXTRA_ENV_RELOC 56 #define CONFIG_ENV_IS_IN_SPI_FLASH 57 #define CONFIG_ENV_SPI_BUS 0 58 #define CONFIG_ENV_SPI_CS 0 59 #define CONFIG_ENV_SPI_MAX_HZ 20000000 60 #define CONFIG_ENV_SPI_MODE 0 61 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ 62 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */ 63 #define CONFIG_ENV_SECT_SIZE 0x010000 64 #define CONFIG_ENV_OFFSET_REDUND 0x110000 65 #define CONFIG_ENV_TOTAL_SIZE 0x020000 66 67 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 68 69 #ifndef __ASSEMBLY__ 70 unsigned long get_board_sys_clk(unsigned long dummy); 71 #endif 72 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_SYS_CACHE_STASHING 78 #define CONFIG_BACKSIDE_L2_CACHE 79 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 80 #define CONFIG_BTB /* toggle branch predition */ 81 82 #define CONFIG_ENABLE_36BIT_PHYS 83 84 #define CONFIG_ADDR_MAP 85 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 86 87 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ 88 89 /* 90 * Config the L3 Cache as L3 SRAM 91 */ 92 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 93 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 94 CONFIG_RAMBOOT_TEXT_BASE) 95 #define CONFIG_SYS_L3_SIZE (1024 << 10) 96 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 97 98 #define CONFIG_SYS_DCSRBAR 0xf0000000 99 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 100 101 /* 102 * DDR Setup 103 */ 104 #define CONFIG_VERY_BIG_RAM 105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 107 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 #define CONFIG_DDR_SPD 112 #define CONFIG_SYS_FSL_DDR3 113 #define CONFIG_FSL_DDR_INTERACTIVE 114 115 #define CONFIG_SYS_SPD_BUS_NUM 0 116 #define SPD_EEPROM_ADDRESS 0x54 117 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 118 119 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 120 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 121 122 /****************************************************************************** 123 * (PRAM usage) 124 * ... ------------------------------------------------------- 125 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM 126 * ... |<------------------- pram -------------------------->| 127 * ... ------------------------------------------------------- 128 * @END_OF_RAM: 129 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose 130 * @CONFIG_KM_PHRAM: address for /var 131 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) 132 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM 133 */ 134 135 /* size of rootfs in RAM */ 136 #define CONFIG_KM_ROOTFSSIZE 0x0 137 /* pseudo-non volatile RAM [hex] */ 138 #define CONFIG_KM_PNVRAM 0x80000 139 /* physical RAM MTD size [hex] */ 140 #define CONFIG_KM_PHRAM 0x100000 141 /* reserved pram area at the end of memory [hex] 142 * u-boot reserves some memory for the MP boot page */ 143 #define CONFIG_KM_RESERVED_PRAM 0x1000 144 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable 145 * is not valid yet, which is the case for when u-boot copies itself to RAM */ 146 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) 147 148 #define CONFIG_KM_CRAMFS_ADDR 0x2000000 149 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ 150 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ 151 152 /* 153 * Local Bus Definitions 154 */ 155 156 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ 157 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) 158 159 /* Nand Flash */ 160 #define CONFIG_NAND_FSL_ELBC 161 #define CONFIG_SYS_NAND_BASE 0xffa00000 162 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 163 164 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 165 #define CONFIG_SYS_MAX_NAND_DEVICE 1 166 #define CONFIG_CMD_NAND 167 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 168 169 #define CONFIG_BCH 170 171 /* NAND flash config */ 172 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 173 | BR_PS_8 /* Port Size = 8 bit */ \ 174 | BR_MS_FCM /* MSEL = FCM */ \ 175 | BR_V) /* valid */ 176 177 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ 178 | OR_FCM_BCTLD /* LBCTL not ass */ \ 179 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ 180 | OR_FCM_RST /* 1 clk read setup */ \ 181 | OR_FCM_PGS /* Large page size */ \ 182 | OR_FCM_CST) /* 0.25 command setup */ 183 184 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 185 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 186 187 /* QRIO FPGA */ 188 #define CONFIG_SYS_QRIO_BASE 0xfb000000 189 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull 190 191 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ 192 | BR_PS_8 /* Port Size 8 bits */ \ 193 | BR_DECC_OFF /* no error corr */ \ 194 | BR_MS_GPCM /* MSEL = GPCM */ \ 195 | BR_V) /* valid */ 196 197 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ 198 | OR_GPCM_BCTLD /* no LCTL assert */ \ 199 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ 200 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ 201 | OR_GPCM_TRLX /* relaxed tmgs */ \ 202 | OR_GPCM_EAD) /* extra bus clk cycles */ 203 204 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ 205 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ 206 207 /* bootcounter in QRIO */ 208 #define CONFIG_BOOTCOUNT_LIMIT 209 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) 210 211 #define CONFIG_BOARD_EARLY_INIT_F 212 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 213 #define CONFIG_MISC_INIT_F 214 #define CONFIG_MISC_INIT_R 215 #define CONFIG_LAST_STAGE_INIT 216 217 #define CONFIG_HWCONFIG 218 219 /* define to use L1 as initial stack */ 220 #define CONFIG_L1_INIT_RAM 221 #define CONFIG_SYS_INIT_RAM_LOCK 222 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 224 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 225 /* The assembler doesn't like typecast */ 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 227 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 228 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 229 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 230 231 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 232 GENERATED_GBL_DATA_SIZE) 233 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 234 235 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 236 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 237 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 238 239 /* Serial Port - controlled on board with jumper J8 240 * open - index 2 241 * shorted - index 1 242 */ 243 #define CONFIG_CONS_INDEX 1 244 #define CONFIG_SYS_NS16550_SERIAL 245 #define CONFIG_SYS_NS16550_REG_SIZE 1 246 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 247 248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 250 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 251 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 252 253 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 254 255 /* I2C */ 256 257 #define CONFIG_SYS_I2C 258 #define CONFIG_SYS_I2C_INIT_BOARD 259 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ 260 #define CONFIG_SYS_NUM_I2C_BUSES 3 261 #define CONFIG_SYS_I2C_MAX_HOPS 1 262 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ 263 #define CONFIG_I2C_MULTI_BUS 264 #define CONFIG_I2C_CMD_TREE 265 #define CONFIG_SYS_FSL_I2C_SPEED 400000 266 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 267 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 268 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ 269 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ 270 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ 271 } 272 #ifndef __ASSEMBLY__ 273 void set_sda(int state); 274 void set_scl(int state); 275 int get_sda(void); 276 int get_scl(void); 277 #endif 278 279 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ 280 281 /* 282 * eSPI - Enhanced SPI 283 */ 284 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ 285 #define CONFIG_SF_DEFAULT_SPEED 20000000 286 #define CONFIG_SF_DEFAULT_MODE 0 287 288 /* 289 * General PCI 290 * Memory space is mapped 1-1, but I/O space must start from 0. 291 */ 292 293 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 294 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 297 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 298 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 299 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 300 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 301 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 302 303 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 304 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 305 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 306 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 307 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 308 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 309 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 310 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull 311 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 312 313 /* Qman/Bman */ 314 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 315 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 316 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 317 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 318 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 319 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 320 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 321 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 322 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 323 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 324 CONFIG_SYS_BMAN_CENA_SIZE) 325 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 326 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 327 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 328 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 329 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 330 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 331 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 332 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 333 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 334 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 335 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 336 CONFIG_SYS_QMAN_CENA_SIZE) 337 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 338 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 339 340 #define CONFIG_SYS_DPAA_FMAN 341 #define CONFIG_SYS_DPAA_PME 342 /* Default address of microcode for the Linux Fman driver 343 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) 344 * ucode is stored after env, so we got 0x120000. 345 */ 346 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 347 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000 348 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 349 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 350 351 #define CONFIG_FMAN_ENET 352 #define CONFIG_PHYLIB_10G 353 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 354 355 #define CONFIG_PCI_INDIRECT_BRIDGE 356 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 357 358 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 359 #define CONFIG_DOS_PARTITION 360 361 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ 362 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 363 #define CONFIG_SYS_TBIPA_VALUE 8 364 #define CONFIG_PHYLIB /* recommended PHY management */ 365 #define CONFIG_ETHPRIME "FM1@DTSEC5" 366 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 367 368 /* 369 * Environment 370 */ 371 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 372 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 373 374 /* 375 * Hardware Watchdog 376 */ 377 #define CONFIG_WATCHDOG /* enable CPU watchdog */ 378 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ 379 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ 380 381 382 /* 383 * additionnal command line configuration. 384 */ 385 #define CONFIG_CMD_PCI 386 #define CONFIG_CMD_ERRATA 387 388 /* we don't need flash support */ 389 #define CONFIG_SYS_NO_FLASH 390 #undef CONFIG_FLASH_CFI_MTD 391 #undef CONFIG_JFFS2_CMDLINE 392 393 /* 394 * For booting Linux, the board info and command line data 395 * have to be in the first 64 MB of memory, since this is 396 * the maximum mapped by the Linux kernel during initialization. 397 */ 398 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 399 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 400 401 #ifdef CONFIG_CMD_KGDB 402 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 403 #endif 404 405 #define __USB_PHY_TYPE utmi 406 #define CONFIG_USB_EHCI_FSL 407 408 /* 409 * Environment Configuration 410 */ 411 #define CONFIG_ENV_OVERWRITE 412 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 413 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 414 #endif 415 416 #ifndef MTDIDS_DEFAULT 417 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" 418 #endif /* MTDIDS_DEFAULT */ 419 420 #ifndef MTDPARTS_DEFAULT 421 # define MTDPARTS_DEFAULT "mtdparts=" \ 422 "fsl_elbc_nand:" \ 423 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 424 #endif /* MTDPARTS_DEFAULT */ 425 426 /* architecture specific default bootargs */ 427 #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" 428 429 /* FIXME: FDT_ADDR is unspecified */ 430 #define CONFIG_KM_DEF_ENV_CPU \ 431 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ 432 "cramfsloadfdt=" \ 433 "cramfsload ${fdt_addr_r} " \ 434 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ 435 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ 436 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ 437 "update=" \ 438 "sf probe 0;sf erase 0 +${filesize};" \ 439 "sf write ${load_addr_r} 0 ${filesize};\0" \ 440 "set_fdthigh=true\0" \ 441 "checkfdt=true\0" \ 442 "" 443 444 #define CONFIG_HW_ENV_SETTINGS \ 445 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ 446 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 447 "usb_dr_mode=host\0" 448 449 #define CONFIG_KM_NEW_ENV \ 450 "newenv=sf probe 0;" \ 451 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ 452 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" 453 454 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ 455 #ifndef CONFIG_KM_DEF_ARCH 456 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 457 #endif 458 459 #define CONFIG_EXTRA_ENV_SETTINGS \ 460 CONFIG_KM_DEF_ENV \ 461 CONFIG_KM_DEF_ARCH \ 462 CONFIG_KM_NEW_ENV \ 463 CONFIG_HW_ENV_SETTINGS \ 464 "EEprom_ivm=pca9547:70:9\0" \ 465 "" 466 467 #endif /* _CONFIG_KMP204X_H */ 468