1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010
4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5  */
6 
7 #ifndef __CONFIG_KM83XX_H
8 #define __CONFIG_KM83XX_H
9 
10 /* include common defines/options for all Keymile boards */
11 #include "keymile-common.h"
12 #include "km-powerpc.h"
13 
14 /*
15  * System Clock Setup
16  */
17 #define CONFIG_83XX_CLKIN		66000000
18 #define CONFIG_SYS_CLK_FREQ		66000000
19 #define CONFIG_83XX_PCICLK		66000000
20 
21 /*
22  * IMMR new address
23  */
24 #define CONFIG_SYS_IMMR		0xE0000000
25 
26 /*
27  * Bus Arbitration Configuration Register (ACR)
28  */
29 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
30 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
31 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
32 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
33 
34 /*
35  * DDR Setup
36  */
37 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
38 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
39 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
40 
41 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
42 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
43 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
44 
45 #define CFG_83XX_DDR_USES_CS0
46 
47 /*
48  * Manually set up DDR parameters
49  */
50 #define CONFIG_DDR_II
51 #define CONFIG_SYS_DDR_SIZE		2048 /* MB */
52 
53 /*
54  * The reserved memory
55  */
56 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
57 #define CONFIG_SYS_FLASH_BASE		0xF0000000
58 
59 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
60 #define CONFIG_SYS_RAMBOOT
61 #endif
62 
63 /* Reserve 768 kB for Mon */
64 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
65 
66 /*
67  * Initial RAM Base Address Setup
68  */
69 #define CONFIG_SYS_INIT_RAM_LOCK
70 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
71 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
72 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
73 						GENERATED_GBL_DATA_SIZE)
74 
75 /*
76  * Init Local Bus Memory Controller:
77  *
78  * Bank Bus     Machine PortSz  Size  Device
79  * ---- ---     ------- ------  -----  ------
80  *  0   Local   GPCM    16 bit  256MB FLASH
81  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
82  *
83  */
84 /*
85  * FLASH on the Local Bus
86  */
87 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
88 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
89 #define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
90 #define CONFIG_SYS_FLASH_PROTECTION
91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
92 
93 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
94 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
95 
96 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
97 				BR_PS_16 | /* 16 bit port size */ \
98 				BR_MS_GPCM | /* MSEL = GPCM */ \
99 				BR_V)
100 
101 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
102 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
103 				OR_GPCM_SCY_5 | \
104 				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
105 
106 #define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
107 #define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
108 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
109 
110 /*
111  * PRIO1/PIGGY on the local bus CS1
112  */
113 /* Window base at flash base */
114 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_KMBEC_FPGA_BASE
115 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)
116 
117 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_KMBEC_FPGA_BASE | \
118 				BR_PS_8 | /* 8 bit port size */ \
119 				BR_MS_GPCM | /* MSEL = GPCM */ \
120 				BR_V)
121 #define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
122 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
123 				OR_GPCM_SCY_2 | \
124 				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
125 
126 /*
127  * Serial Port
128  */
129 #define CONFIG_SYS_NS16550_SERIAL
130 #define CONFIG_SYS_NS16550_REG_SIZE	1
131 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
132 
133 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
134 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
135 
136 /*
137  * QE UEC ethernet configuration
138  */
139 #define CONFIG_UEC_ETH
140 #define CONFIG_ETHPRIME		"UEC0"
141 
142 #if !defined(CONFIG_MPC8309)
143 #define CONFIG_UEC_ETH1		/* GETH1 */
144 #define UEC_VERBOSE_DEBUG	1
145 #endif
146 
147 #ifdef CONFIG_UEC_ETH1
148 #define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
149 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
150 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
151 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
152 #define CONFIG_SYS_UEC1_PHY_ADDR	0
153 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
154 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
155 #endif
156 
157 /*
158  * Environment
159  */
160 
161 #ifndef CONFIG_SYS_RAMBOOT
162 #ifndef CONFIG_ENV_ADDR
163 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
164 					CONFIG_SYS_MONITOR_LEN)
165 #endif
166 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
167 #ifndef CONFIG_ENV_OFFSET
168 #define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
169 #endif
170 
171 /* Address and size of Redundant Environment Sector	*/
172 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
173 						CONFIG_ENV_SECT_SIZE)
174 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
175 
176 #else /* CFG_SYS_RAMBOOT */
177 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
178 #define CONFIG_ENV_SIZE		0x2000
179 #endif /* CFG_SYS_RAMBOOT */
180 
181 /* I2C */
182 #define CONFIG_SYS_I2C
183 #define CONFIG_SYS_NUM_I2C_BUSES	4
184 #define CONFIG_SYS_I2C_MAX_HOPS		1
185 #define CONFIG_SYS_I2C_FSL
186 #define CONFIG_SYS_FSL_I2C_SPEED	200000
187 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
188 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
189 #define CONFIG_SYS_I2C_OFFSET		0x3000
190 #define CONFIG_SYS_FSL_I2C2_SPEED	200000
191 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
192 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
193 #define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
194 		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
195 		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
196 		{1, {I2C_NULL_HOP} } }
197 
198 #define CONFIG_KM_IVM_BUS		2	/* I2C2 (Mux-Port 1)*/
199 
200 #if defined(CONFIG_CMD_NAND)
201 #define CONFIG_NAND_KMETER1
202 #define CONFIG_SYS_MAX_NAND_DEVICE	1
203 #define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
204 #endif
205 
206 /*
207  * For booting Linux, the board info and command line data
208  * have to be in the first 8 MB of memory, since this is
209  * the maximum mapped by the Linux kernel during initialization.
210  */
211 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
212 
213 /*
214  * Core HID Setup
215  */
216 #define CONFIG_SYS_HID0_INIT		0x000000000
217 #define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
218 					 HID0_ENABLE_INSTRUCTION_CACHE)
219 #define CONFIG_SYS_HID2			HID2_HBE
220 
221 /*
222  * MMU Setup
223  */
224 
225 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
226 
227 /* DDR: cache cacheable */
228 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
229 				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
230 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
231 					BATU_VS | BATU_VP)
232 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
233 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
234 
235 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
236 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
237 				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
238 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
239 					| BATU_VP)
240 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
241 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
242 
243 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
244 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
245 				BATL_MEMCOHERENCE)
246 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
247 				BATU_VS | BATU_VP)
248 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
249 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
250 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
251 
252 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
253 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
254 					BATL_MEMCOHERENCE)
255 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
256 					BATU_VS | BATU_VP)
257 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
258 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
259 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
260 
261 /* Stack in dcache: cacheable, no memory coherence */
262 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
263 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
264 					BATU_VS | BATU_VP)
265 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
266 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
267 
268 /*
269  * Internal Definitions
270  */
271 #define BOOTFLASH_START	0xF0000000
272 
273 #define CONFIG_KM_CONSOLE_TTY	"ttyS0"
274 
275 /*
276  * Environment Configuration
277  */
278 #define CONFIG_ENV_OVERWRITE
279 #ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
280 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
281 #endif
282 
283 #ifndef CONFIG_KM_DEF_ARCH
284 #define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
285 #endif
286 
287 #define CONFIG_EXTRA_ENV_SETTINGS \
288 	CONFIG_KM_DEF_ENV						\
289 	CONFIG_KM_DEF_ARCH						\
290 	"newenv="							\
291 		"prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "	\
292 		"era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"		\
293 	"unlock=yes\0"							\
294 	""
295 
296 #if defined(CONFIG_UEC_ETH)
297 #define CONFIG_HAS_ETH0
298 #endif
299 
300 #endif /* __CONFIG_KM83XX_H */
301