1 /* 2 * (C) Copyright 2010 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_KM83XX_H 9 #define __CONFIG_KM83XX_H 10 11 #define CONFIG_DISPLAY_BOARDINFO 12 13 /* include common defines/options for all Keymile boards */ 14 #include "keymile-common.h" 15 #include "km-powerpc.h" 16 17 #ifndef MTDIDS_DEFAULT 18 # define MTDIDS_DEFAULT "nor0=boot" 19 #endif /* MTDIDS_DEFAULT */ 20 21 #ifndef MTDPARTS_DEFAULT 22 # define MTDPARTS_DEFAULT "mtdparts=" \ 23 "boot:" \ 24 "768k(u-boot)," \ 25 "128k(env)," \ 26 "128k(envred)," \ 27 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 28 #endif /* MTDPARTS_DEFAULT */ 29 30 #define CONFIG_MISC_INIT_R 31 /* 32 * System Clock Setup 33 */ 34 #define CONFIG_83XX_CLKIN 66000000 35 #define CONFIG_SYS_CLK_FREQ 66000000 36 #define CONFIG_83XX_PCICLK 66000000 37 38 /* 39 * IMMR new address 40 */ 41 #define CONFIG_SYS_IMMR 0xE0000000 42 43 /* 44 * Bus Arbitration Configuration Register (ACR) 45 */ 46 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 47 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 48 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 49 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 50 51 /* 52 * DDR Setup 53 */ 54 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 56 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 57 58 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 59 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 60 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 61 62 #define CFG_83XX_DDR_USES_CS0 63 64 /* 65 * Manually set up DDR parameters 66 */ 67 #define CONFIG_DDR_II 68 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 69 70 /* 71 * The reserved memory 72 */ 73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 74 #define CONFIG_SYS_FLASH_BASE 0xF0000000 75 76 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 77 #define CONFIG_SYS_RAMBOOT 78 #endif 79 80 /* Reserve 768 kB for Mon */ 81 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 82 83 /* 84 * Initial RAM Base Address Setup 85 */ 86 #define CONFIG_SYS_INIT_RAM_LOCK 87 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 88 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 89 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 90 GENERATED_GBL_DATA_SIZE) 91 92 /* 93 * Init Local Bus Memory Controller: 94 * 95 * Bank Bus Machine PortSz Size Device 96 * ---- --- ------- ------ ----- ------ 97 * 0 Local GPCM 16 bit 256MB FLASH 98 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 99 * 100 */ 101 /* 102 * FLASH on the Local Bus 103 */ 104 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 105 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 106 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 107 #define CONFIG_SYS_FLASH_PROTECTION 108 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 109 110 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 111 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 112 113 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 114 BR_PS_16 | /* 16 bit port size */ \ 115 BR_MS_GPCM | /* MSEL = GPCM */ \ 116 BR_V) 117 118 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 119 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 120 OR_GPCM_SCY_5 | \ 121 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 122 123 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 124 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 125 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 126 127 /* 128 * PRIO1/PIGGY on the local bus CS1 129 */ 130 /* Window base at flash base */ 131 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 132 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 133 134 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 135 BR_PS_8 | /* 8 bit port size */ \ 136 BR_MS_GPCM | /* MSEL = GPCM */ \ 137 BR_V) 138 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 139 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 140 OR_GPCM_SCY_2 | \ 141 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 142 143 /* 144 * Serial Port 145 */ 146 #define CONFIG_CONS_INDEX 1 147 #define CONFIG_SYS_NS16550_SERIAL 148 #define CONFIG_SYS_NS16550_REG_SIZE 1 149 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 150 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 153 154 #define CONFIG_OF_STDOUT_VIA_ALIAS 155 156 /* 157 * QE UEC ethernet configuration 158 */ 159 #define CONFIG_UEC_ETH 160 #define CONFIG_ETHPRIME "UEC0" 161 162 #if !defined(CONFIG_MPC8309) 163 #define CONFIG_UEC_ETH1 /* GETH1 */ 164 #define UEC_VERBOSE_DEBUG 1 165 #endif 166 167 #ifdef CONFIG_UEC_ETH1 168 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 169 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 170 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 171 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 172 #define CONFIG_SYS_UEC1_PHY_ADDR 0 173 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 174 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 175 #endif 176 177 /* 178 * Environment 179 */ 180 181 #ifndef CONFIG_SYS_RAMBOOT 182 #define CONFIG_ENV_IS_IN_FLASH 183 #ifndef CONFIG_ENV_ADDR 184 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 185 CONFIG_SYS_MONITOR_LEN) 186 #endif 187 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 188 #ifndef CONFIG_ENV_OFFSET 189 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 190 #endif 191 192 /* Address and size of Redundant Environment Sector */ 193 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 194 CONFIG_ENV_SECT_SIZE) 195 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 196 197 #else /* CFG_SYS_RAMBOOT */ 198 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 199 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 200 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 201 #define CONFIG_ENV_SIZE 0x2000 202 #endif /* CFG_SYS_RAMBOOT */ 203 204 /* I2C */ 205 #define CONFIG_SYS_I2C 206 #define CONFIG_SYS_NUM_I2C_BUSES 4 207 #define CONFIG_SYS_I2C_MAX_HOPS 1 208 #define CONFIG_SYS_I2C_FSL 209 #define CONFIG_SYS_FSL_I2C_SPEED 200000 210 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 211 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 212 #define CONFIG_SYS_I2C_OFFSET 0x3000 213 #define CONFIG_SYS_FSL_I2C2_SPEED 200000 214 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 216 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ 217 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 218 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 219 {1, {I2C_NULL_HOP} } } 220 221 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ 222 223 /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 224 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 225 #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 226 #define CONFIG_SYS_DTT_MAX_TEMP 70 227 #define CONFIG_SYS_DTT_HYSTERESIS 3 228 #define CONFIG_SYS_DTT_BUS_NUM 1 229 230 #if defined(CONFIG_CMD_NAND) 231 #define CONFIG_NAND_KMETER1 232 #define CONFIG_SYS_MAX_NAND_DEVICE 1 233 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 234 #endif 235 236 #if defined(CONFIG_PCI) 237 #define CONFIG_CMD_PCI 238 #endif 239 240 /* 241 * For booting Linux, the board info and command line data 242 * have to be in the first 8 MB of memory, since this is 243 * the maximum mapped by the Linux kernel during initialization. 244 */ 245 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 246 247 /* 248 * Core HID Setup 249 */ 250 #define CONFIG_SYS_HID0_INIT 0x000000000 251 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 252 HID0_ENABLE_INSTRUCTION_CACHE) 253 #define CONFIG_SYS_HID2 HID2_HBE 254 255 /* 256 * MMU Setup 257 */ 258 259 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 260 261 /* DDR: cache cacheable */ 262 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 263 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 264 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 265 BATU_VS | BATU_VP) 266 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 267 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 268 269 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 270 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 271 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 272 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 273 | BATU_VP) 274 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 275 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 276 277 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 278 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 279 BATL_MEMCOHERENCE) 280 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 281 BATU_VS | BATU_VP) 282 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 283 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 284 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 285 286 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 287 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 288 BATL_MEMCOHERENCE) 289 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 290 BATU_VS | BATU_VP) 291 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 292 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 293 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 294 295 /* Stack in dcache: cacheable, no memory coherence */ 296 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 297 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 298 BATU_VS | BATU_VP) 299 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 300 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 301 302 /* 303 * Internal Definitions 304 */ 305 #define BOOTFLASH_START 0xF0000000 306 307 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 308 309 /* 310 * Environment Configuration 311 */ 312 #define CONFIG_ENV_OVERWRITE 313 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 314 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 315 #endif 316 317 #ifndef CONFIG_KM_DEF_ARCH 318 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 319 #endif 320 321 #define CONFIG_EXTRA_ENV_SETTINGS \ 322 CONFIG_KM_DEF_ENV \ 323 CONFIG_KM_DEF_ARCH \ 324 "newenv=" \ 325 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ 326 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ 327 "unlock=yes\0" \ 328 "" 329 330 #if defined(CONFIG_UEC_ETH) 331 #define CONFIG_HAS_ETH0 332 #endif 333 334 #endif /* __CONFIG_KM83XX_H */ 335