1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 */ 6 7 #ifndef __CONFIG_KM83XX_H 8 #define __CONFIG_KM83XX_H 9 10 /* include common defines/options for all Keymile boards */ 11 #include "keymile-common.h" 12 #include "km-powerpc.h" 13 14 /* 15 * System Clock Setup 16 */ 17 #define CONFIG_83XX_CLKIN 66000000 18 #define CONFIG_SYS_CLK_FREQ 66000000 19 #define CONFIG_83XX_PCICLK 66000000 20 21 /* 22 * IMMR new address 23 */ 24 #define CONFIG_SYS_IMMR 0xE0000000 25 26 /* 27 * Bus Arbitration Configuration Register (ACR) 28 */ 29 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 30 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 31 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 32 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 33 34 /* 35 * DDR Setup 36 */ 37 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 39 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 40 41 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 42 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 43 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 44 45 #define CFG_83XX_DDR_USES_CS0 46 47 /* 48 * Manually set up DDR parameters 49 */ 50 #define CONFIG_DDR_II 51 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 52 53 /* 54 * The reserved memory 55 */ 56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 57 #define CONFIG_SYS_FLASH_BASE 0xF0000000 58 59 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 60 #define CONFIG_SYS_RAMBOOT 61 #endif 62 63 /* Reserve 768 kB for Mon */ 64 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 65 66 /* 67 * Initial RAM Base Address Setup 68 */ 69 #define CONFIG_SYS_INIT_RAM_LOCK 70 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 71 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 72 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 73 GENERATED_GBL_DATA_SIZE) 74 75 /* 76 * Init Local Bus Memory Controller: 77 * 78 * Bank Bus Machine PortSz Size Device 79 * ---- --- ------- ------ ----- ------ 80 * 0 Local GPCM 16 bit 256MB FLASH 81 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 82 * 83 */ 84 /* 85 * FLASH on the Local Bus 86 */ 87 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 88 89 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 90 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 91 92 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 93 BR_PS_16 | /* 16 bit port size */ \ 94 BR_MS_GPCM | /* MSEL = GPCM */ \ 95 BR_V) 96 97 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 98 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 99 OR_GPCM_SCY_5 | \ 100 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 101 102 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 103 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 104 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 105 106 /* 107 * PRIO1/PIGGY on the local bus CS1 108 */ 109 /* Window base at flash base */ 110 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 111 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 112 113 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 114 BR_PS_8 | /* 8 bit port size */ \ 115 BR_MS_GPCM | /* MSEL = GPCM */ \ 116 BR_V) 117 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 118 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 119 OR_GPCM_SCY_2 | \ 120 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 121 122 /* 123 * Serial Port 124 */ 125 #define CONFIG_SYS_NS16550_SERIAL 126 #define CONFIG_SYS_NS16550_REG_SIZE 1 127 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 128 129 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 130 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 131 132 /* 133 * QE UEC ethernet configuration 134 */ 135 #define CONFIG_UEC_ETH 136 #define CONFIG_ETHPRIME "UEC0" 137 138 #if !defined(CONFIG_MPC8309) 139 #define CONFIG_UEC_ETH1 /* GETH1 */ 140 #define UEC_VERBOSE_DEBUG 1 141 #endif 142 143 #ifdef CONFIG_UEC_ETH1 144 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 145 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 146 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 147 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 148 #define CONFIG_SYS_UEC1_PHY_ADDR 0 149 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 150 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 151 #endif 152 153 /* 154 * Environment 155 */ 156 157 #ifndef CONFIG_SYS_RAMBOOT 158 #ifndef CONFIG_ENV_ADDR 159 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 160 CONFIG_SYS_MONITOR_LEN) 161 #endif 162 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 163 #ifndef CONFIG_ENV_OFFSET 164 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 165 #endif 166 167 /* Address and size of Redundant Environment Sector */ 168 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 169 CONFIG_ENV_SECT_SIZE) 170 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 171 172 #else /* CFG_SYS_RAMBOOT */ 173 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 174 #define CONFIG_ENV_SIZE 0x2000 175 #endif /* CFG_SYS_RAMBOOT */ 176 177 /* I2C */ 178 #define CONFIG_SYS_I2C 179 #define CONFIG_SYS_NUM_I2C_BUSES 4 180 #define CONFIG_SYS_I2C_MAX_HOPS 1 181 #define CONFIG_SYS_I2C_FSL 182 #define CONFIG_SYS_FSL_I2C_SPEED 200000 183 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 184 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 185 #define CONFIG_SYS_I2C_OFFSET 0x3000 186 #define CONFIG_SYS_FSL_I2C2_SPEED 200000 187 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 188 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 189 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ 190 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 191 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 192 {1, {I2C_NULL_HOP} } } 193 194 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ 195 196 #if defined(CONFIG_CMD_NAND) 197 #define CONFIG_NAND_KMETER1 198 #define CONFIG_SYS_MAX_NAND_DEVICE 1 199 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 200 #endif 201 202 /* 203 * For booting Linux, the board info and command line data 204 * have to be in the first 8 MB of memory, since this is 205 * the maximum mapped by the Linux kernel during initialization. 206 */ 207 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 208 209 /* 210 * Core HID Setup 211 */ 212 #define CONFIG_SYS_HID0_INIT 0x000000000 213 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 214 HID0_ENABLE_INSTRUCTION_CACHE) 215 #define CONFIG_SYS_HID2 HID2_HBE 216 217 /* 218 * MMU Setup 219 */ 220 221 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 222 223 /* DDR: cache cacheable */ 224 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 225 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 226 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 227 BATU_VS | BATU_VP) 228 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 229 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 230 231 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 232 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 233 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 234 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 235 | BATU_VP) 236 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 237 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 238 239 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 240 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 241 BATL_MEMCOHERENCE) 242 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 243 BATU_VS | BATU_VP) 244 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 245 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 246 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 247 248 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 249 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 250 BATL_MEMCOHERENCE) 251 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 252 BATU_VS | BATU_VP) 253 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 254 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 255 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 256 257 /* Stack in dcache: cacheable, no memory coherence */ 258 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 259 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 260 BATU_VS | BATU_VP) 261 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 262 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 263 264 /* 265 * Internal Definitions 266 */ 267 #define BOOTFLASH_START 0xF0000000 268 269 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 270 271 /* 272 * Environment Configuration 273 */ 274 #define CONFIG_ENV_OVERWRITE 275 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 276 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 277 #endif 278 279 #ifndef CONFIG_KM_DEF_ARCH 280 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 281 #endif 282 283 #define CONFIG_EXTRA_ENV_SETTINGS \ 284 CONFIG_KM_DEF_ENV \ 285 CONFIG_KM_DEF_ARCH \ 286 "newenv=" \ 287 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ 288 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ 289 "unlock=yes\0" \ 290 "" 291 292 #if defined(CONFIG_UEC_ETH) 293 #define CONFIG_HAS_ETH0 294 #endif 295 296 #endif /* __CONFIG_KM83XX_H */ 297