1 /* 2 * (C) Copyright 2010 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_KM83XX_H 9 #define __CONFIG_KM83XX_H 10 11 /* include common defines/options for all Keymile boards */ 12 #include "keymile-common.h" 13 #include "km-powerpc.h" 14 15 #ifndef MTDIDS_DEFAULT 16 # define MTDIDS_DEFAULT "nor0=boot" 17 #endif /* MTDIDS_DEFAULT */ 18 19 #ifndef MTDPARTS_DEFAULT 20 # define MTDPARTS_DEFAULT "mtdparts=" \ 21 "boot:" \ 22 "768k(u-boot)," \ 23 "128k(env)," \ 24 "128k(envred)," \ 25 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 26 #endif /* MTDPARTS_DEFAULT */ 27 28 #define CONFIG_MISC_INIT_R 29 /* 30 * System Clock Setup 31 */ 32 #define CONFIG_83XX_CLKIN 66000000 33 #define CONFIG_SYS_CLK_FREQ 66000000 34 #define CONFIG_83XX_PCICLK 66000000 35 36 /* 37 * IMMR new address 38 */ 39 #define CONFIG_SYS_IMMR 0xE0000000 40 41 /* 42 * Bus Arbitration Configuration Register (ACR) 43 */ 44 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 45 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 46 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 47 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 48 49 /* 50 * DDR Setup 51 */ 52 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 53 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 54 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 55 56 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 57 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 58 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 59 60 #define CFG_83XX_DDR_USES_CS0 61 62 /* 63 * Manually set up DDR parameters 64 */ 65 #define CONFIG_DDR_II 66 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 67 68 /* 69 * The reserved memory 70 */ 71 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 72 #define CONFIG_SYS_FLASH_BASE 0xF0000000 73 74 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 75 #define CONFIG_SYS_RAMBOOT 76 #endif 77 78 /* Reserve 768 kB for Mon */ 79 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 80 81 /* 82 * Initial RAM Base Address Setup 83 */ 84 #define CONFIG_SYS_INIT_RAM_LOCK 85 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 86 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 87 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 88 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 89 GENERATED_GBL_DATA_SIZE) 90 91 /* 92 * Init Local Bus Memory Controller: 93 * 94 * Bank Bus Machine PortSz Size Device 95 * ---- --- ------- ------ ----- ------ 96 * 0 Local GPCM 16 bit 256MB FLASH 97 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 98 * 99 */ 100 /* 101 * FLASH on the Local Bus 102 */ 103 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 104 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 105 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 106 #define CONFIG_SYS_FLASH_PROTECTION 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 108 109 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 110 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 111 112 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 113 BR_PS_16 | /* 16 bit port size */ \ 114 BR_MS_GPCM | /* MSEL = GPCM */ \ 115 BR_V) 116 117 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 118 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 119 OR_GPCM_SCY_5 | \ 120 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 121 122 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 123 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 124 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 125 126 /* 127 * PRIO1/PIGGY on the local bus CS1 128 */ 129 /* Window base at flash base */ 130 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 131 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 132 133 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 134 BR_PS_8 | /* 8 bit port size */ \ 135 BR_MS_GPCM | /* MSEL = GPCM */ \ 136 BR_V) 137 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 138 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 139 OR_GPCM_SCY_2 | \ 140 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 141 142 /* 143 * Serial Port 144 */ 145 #define CONFIG_CONS_INDEX 1 146 #define CONFIG_SYS_NS16550 147 #define CONFIG_SYS_NS16550_SERIAL 148 #define CONFIG_SYS_NS16550_REG_SIZE 1 149 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 150 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 153 154 /* Pass open firmware flat tree */ 155 #define CONFIG_OF_LIBFDT 156 #define CONFIG_OF_BOARD_SETUP 157 #define CONFIG_OF_STDOUT_VIA_ALIAS 158 159 /* 160 * QE UEC ethernet configuration 161 */ 162 #define CONFIG_UEC_ETH 163 #define CONFIG_ETHPRIME "UEC0" 164 165 #if !defined(CONFIG_MPC8309) 166 #define CONFIG_UEC_ETH1 /* GETH1 */ 167 #define UEC_VERBOSE_DEBUG 1 168 #endif 169 170 #ifdef CONFIG_UEC_ETH1 171 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 172 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 173 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 174 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 175 #define CONFIG_SYS_UEC1_PHY_ADDR 0 176 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 177 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 178 #endif 179 180 /* 181 * Environment 182 */ 183 184 #ifndef CONFIG_SYS_RAMBOOT 185 #define CONFIG_ENV_IS_IN_FLASH 186 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 187 CONFIG_SYS_MONITOR_LEN) 188 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 189 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 190 191 /* Address and size of Redundant Environment Sector */ 192 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 193 CONFIG_ENV_SECT_SIZE) 194 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 195 196 #else /* CFG_SYS_RAMBOOT */ 197 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 198 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 199 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 200 #define CONFIG_ENV_SIZE 0x2000 201 #endif /* CFG_SYS_RAMBOOT */ 202 203 /* I2C */ 204 #define CONFIG_SYS_I2C 205 #define CONFIG_SYS_NUM_I2C_BUSES 4 206 #define CONFIG_SYS_I2C_MAX_HOPS 1 207 #define CONFIG_SYS_I2C_FSL 208 #define CONFIG_SYS_FSL_I2C_SPEED 200000 209 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 211 #define CONFIG_SYS_I2C_OFFSET 0x3000 212 #define CONFIG_SYS_FSL_I2C2_SPEED 200000 213 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 214 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 215 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ 216 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 217 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 218 {1, {I2C_NULL_HOP} } } 219 220 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ 221 222 /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 223 #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 224 #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 225 #define CONFIG_SYS_DTT_MAX_TEMP 70 226 #define CONFIG_SYS_DTT_HYSTERESIS 3 227 #define CONFIG_SYS_DTT_BUS_NUM 1 228 229 #if defined(CONFIG_CMD_NAND) 230 #define CONFIG_NAND_KMETER1 231 #define CONFIG_SYS_MAX_NAND_DEVICE 1 232 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 233 #endif 234 235 #if defined(CONFIG_PCI) 236 #define CONFIG_CMD_PCI 237 #endif 238 239 /* 240 * For booting Linux, the board info and command line data 241 * have to be in the first 8 MB of memory, since this is 242 * the maximum mapped by the Linux kernel during initialization. 243 */ 244 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 245 246 /* 247 * Core HID Setup 248 */ 249 #define CONFIG_SYS_HID0_INIT 0x000000000 250 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 251 HID0_ENABLE_INSTRUCTION_CACHE) 252 #define CONFIG_SYS_HID2 HID2_HBE 253 254 /* 255 * MMU Setup 256 */ 257 258 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 259 260 /* DDR: cache cacheable */ 261 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 262 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 263 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 264 BATU_VS | BATU_VP) 265 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 266 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 267 268 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 269 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 270 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 271 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 272 | BATU_VP) 273 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 274 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 275 276 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 277 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 278 BATL_MEMCOHERENCE) 279 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 280 BATU_VS | BATU_VP) 281 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 282 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 283 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 284 285 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 286 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 287 BATL_MEMCOHERENCE) 288 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 289 BATU_VS | BATU_VP) 290 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 291 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 292 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 293 294 /* Stack in dcache: cacheable, no memory coherence */ 295 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 296 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 297 BATU_VS | BATU_VP) 298 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 299 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 300 301 /* 302 * Internal Definitions 303 */ 304 #define BOOTFLASH_START 0xF0000000 305 306 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 307 308 /* 309 * Environment Configuration 310 */ 311 #define CONFIG_ENV_OVERWRITE 312 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 313 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 314 #endif 315 316 #ifndef CONFIG_KM_DEF_ARCH 317 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 318 #endif 319 320 #define CONFIG_EXTRA_ENV_SETTINGS \ 321 CONFIG_KM_DEF_ENV \ 322 CONFIG_KM_DEF_ARCH \ 323 "newenv=" \ 324 "prot off 0xF00C0000 +0x40000 && " \ 325 "era 0xF00C0000 +0x40000\0" \ 326 "unlock=yes\0" \ 327 "" 328 329 #if defined(CONFIG_UEC_ETH) 330 #define CONFIG_HAS_ETH0 331 #endif 332 333 #endif /* __CONFIG_KM83XX_H */ 334