1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 */ 6 7 #ifndef __CONFIG_KM83XX_H 8 #define __CONFIG_KM83XX_H 9 10 /* include common defines/options for all Keymile boards */ 11 #include "keymile-common.h" 12 #include "km-powerpc.h" 13 14 #define CONFIG_MISC_INIT_R 15 /* 16 * System Clock Setup 17 */ 18 #define CONFIG_83XX_CLKIN 66000000 19 #define CONFIG_SYS_CLK_FREQ 66000000 20 #define CONFIG_83XX_PCICLK 66000000 21 22 /* 23 * IMMR new address 24 */ 25 #define CONFIG_SYS_IMMR 0xE0000000 26 27 /* 28 * Bus Arbitration Configuration Register (ACR) 29 */ 30 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 31 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 32 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 33 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 34 35 /* 36 * DDR Setup 37 */ 38 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 39 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 40 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 41 42 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 43 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 44 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 45 46 #define CFG_83XX_DDR_USES_CS0 47 48 /* 49 * Manually set up DDR parameters 50 */ 51 #define CONFIG_DDR_II 52 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 53 54 /* 55 * The reserved memory 56 */ 57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 58 #define CONFIG_SYS_FLASH_BASE 0xF0000000 59 60 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 61 #define CONFIG_SYS_RAMBOOT 62 #endif 63 64 /* Reserve 768 kB for Mon */ 65 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 66 67 /* 68 * Initial RAM Base Address Setup 69 */ 70 #define CONFIG_SYS_INIT_RAM_LOCK 71 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 72 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 73 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 74 GENERATED_GBL_DATA_SIZE) 75 76 /* 77 * Init Local Bus Memory Controller: 78 * 79 * Bank Bus Machine PortSz Size Device 80 * ---- --- ------- ------ ----- ------ 81 * 0 Local GPCM 16 bit 256MB FLASH 82 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 83 * 84 */ 85 /* 86 * FLASH on the Local Bus 87 */ 88 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 89 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 90 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 91 #define CONFIG_SYS_FLASH_PROTECTION 92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 93 94 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 95 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 96 97 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 98 BR_PS_16 | /* 16 bit port size */ \ 99 BR_MS_GPCM | /* MSEL = GPCM */ \ 100 BR_V) 101 102 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 103 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 104 OR_GPCM_SCY_5 | \ 105 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 106 107 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 108 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 109 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 110 111 /* 112 * PRIO1/PIGGY on the local bus CS1 113 */ 114 /* Window base at flash base */ 115 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 116 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 117 118 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 119 BR_PS_8 | /* 8 bit port size */ \ 120 BR_MS_GPCM | /* MSEL = GPCM */ \ 121 BR_V) 122 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 123 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 124 OR_GPCM_SCY_2 | \ 125 OR_GPCM_TRLX_SET | OR_GPCM_EAD) 126 127 /* 128 * Serial Port 129 */ 130 #define CONFIG_SYS_NS16550_SERIAL 131 #define CONFIG_SYS_NS16550_REG_SIZE 1 132 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 133 134 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 135 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 136 137 /* 138 * QE UEC ethernet configuration 139 */ 140 #define CONFIG_UEC_ETH 141 #define CONFIG_ETHPRIME "UEC0" 142 143 #if !defined(CONFIG_MPC8309) 144 #define CONFIG_UEC_ETH1 /* GETH1 */ 145 #define UEC_VERBOSE_DEBUG 1 146 #endif 147 148 #ifdef CONFIG_UEC_ETH1 149 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 150 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 151 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 152 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 153 #define CONFIG_SYS_UEC1_PHY_ADDR 0 154 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 155 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 156 #endif 157 158 /* 159 * Environment 160 */ 161 162 #ifndef CONFIG_SYS_RAMBOOT 163 #ifndef CONFIG_ENV_ADDR 164 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 165 CONFIG_SYS_MONITOR_LEN) 166 #endif 167 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 168 #ifndef CONFIG_ENV_OFFSET 169 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 170 #endif 171 172 /* Address and size of Redundant Environment Sector */ 173 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 174 CONFIG_ENV_SECT_SIZE) 175 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 176 177 #else /* CFG_SYS_RAMBOOT */ 178 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 179 #define CONFIG_ENV_SIZE 0x2000 180 #endif /* CFG_SYS_RAMBOOT */ 181 182 /* I2C */ 183 #define CONFIG_SYS_I2C 184 #define CONFIG_SYS_NUM_I2C_BUSES 4 185 #define CONFIG_SYS_I2C_MAX_HOPS 1 186 #define CONFIG_SYS_I2C_FSL 187 #define CONFIG_SYS_FSL_I2C_SPEED 200000 188 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 189 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 190 #define CONFIG_SYS_I2C_OFFSET 0x3000 191 #define CONFIG_SYS_FSL_I2C2_SPEED 200000 192 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 193 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 194 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ 195 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 196 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 197 {1, {I2C_NULL_HOP} } } 198 199 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ 200 201 #if defined(CONFIG_CMD_NAND) 202 #define CONFIG_NAND_KMETER1 203 #define CONFIG_SYS_MAX_NAND_DEVICE 1 204 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 205 #endif 206 207 /* 208 * For booting Linux, the board info and command line data 209 * have to be in the first 8 MB of memory, since this is 210 * the maximum mapped by the Linux kernel during initialization. 211 */ 212 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 213 214 /* 215 * Core HID Setup 216 */ 217 #define CONFIG_SYS_HID0_INIT 0x000000000 218 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 219 HID0_ENABLE_INSTRUCTION_CACHE) 220 #define CONFIG_SYS_HID2 HID2_HBE 221 222 /* 223 * MMU Setup 224 */ 225 226 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 227 228 /* DDR: cache cacheable */ 229 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 230 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 231 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 232 BATU_VS | BATU_VP) 233 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 234 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 235 236 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 237 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 238 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 239 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 240 | BATU_VP) 241 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 242 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 243 244 /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 245 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 246 BATL_MEMCOHERENCE) 247 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 248 BATU_VS | BATU_VP) 249 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 250 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 251 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 252 253 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 254 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 255 BATL_MEMCOHERENCE) 256 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 257 BATU_VS | BATU_VP) 258 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 259 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 260 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 261 262 /* Stack in dcache: cacheable, no memory coherence */ 263 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 264 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 265 BATU_VS | BATU_VP) 266 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 267 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 268 269 /* 270 * Internal Definitions 271 */ 272 #define BOOTFLASH_START 0xF0000000 273 274 #define CONFIG_KM_CONSOLE_TTY "ttyS0" 275 276 /* 277 * Environment Configuration 278 */ 279 #define CONFIG_ENV_OVERWRITE 280 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 281 #define CONFIG_KM_DEF_ENV "km-common=empty\0" 282 #endif 283 284 #ifndef CONFIG_KM_DEF_ARCH 285 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 286 #endif 287 288 #define CONFIG_EXTRA_ENV_SETTINGS \ 289 CONFIG_KM_DEF_ENV \ 290 CONFIG_KM_DEF_ARCH \ 291 "newenv=" \ 292 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ 293 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ 294 "unlock=yes\0" \ 295 "" 296 297 #if defined(CONFIG_UEC_ETH) 298 #define CONFIG_HAS_ETH0 299 #endif 300 301 #endif /* __CONFIG_KM83XX_H */ 302