1264eaa0eSValentin Longchamp /* 2264eaa0eSValentin Longchamp * (C) Copyright 2010 3264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4264eaa0eSValentin Longchamp * 5264eaa0eSValentin Longchamp * This program is free software; you can redistribute it and/or 6264eaa0eSValentin Longchamp * modify it under the terms of the GNU General Public License as 7264eaa0eSValentin Longchamp * published by the Free Software Foundation; either version 2 of 8264eaa0eSValentin Longchamp * the License, or (at your option) any later version. 9264eaa0eSValentin Longchamp */ 10264eaa0eSValentin Longchamp 11264eaa0eSValentin Longchamp #ifndef __CONFIG_KM83XX_H 12264eaa0eSValentin Longchamp #define __CONFIG_KM83XX_H 13264eaa0eSValentin Longchamp 14264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */ 15264eaa0eSValentin Longchamp #include "keymile-common.h" 16264eaa0eSValentin Longchamp #include "km-powerpc.h" 17264eaa0eSValentin Longchamp 18264eaa0eSValentin Longchamp #define MTDIDS_DEFAULT "nor0=boot" 19264eaa0eSValentin Longchamp #define MTDPARTS_DEFAULT "mtdparts=" \ 20264eaa0eSValentin Longchamp "boot:" \ 21264eaa0eSValentin Longchamp "768k(u-boot)," \ 22264eaa0eSValentin Longchamp "128k(env)," \ 23264eaa0eSValentin Longchamp "128k(envred)," \ 24264eaa0eSValentin Longchamp "-(" CONFIG_KM_UBI_PARTITION_NAME ")" 25264eaa0eSValentin Longchamp 26264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R 27264eaa0eSValentin Longchamp /* 28264eaa0eSValentin Longchamp * System Clock Setup 29264eaa0eSValentin Longchamp */ 30264eaa0eSValentin Longchamp #define CONFIG_83XX_CLKIN 66000000 31264eaa0eSValentin Longchamp #define CONFIG_SYS_CLK_FREQ 66000000 32264eaa0eSValentin Longchamp #define CONFIG_83XX_PCICLK 66000000 33264eaa0eSValentin Longchamp 34264eaa0eSValentin Longchamp /* 35264eaa0eSValentin Longchamp * IMMR new address 36264eaa0eSValentin Longchamp */ 37264eaa0eSValentin Longchamp #define CONFIG_SYS_IMMR 0xE0000000 38264eaa0eSValentin Longchamp 39264eaa0eSValentin Longchamp /* 40264eaa0eSValentin Longchamp * Bus Arbitration Configuration Register (ACR) 41264eaa0eSValentin Longchamp */ 42264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 43264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 44264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 45264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 46264eaa0eSValentin Longchamp 47264eaa0eSValentin Longchamp /* 48264eaa0eSValentin Longchamp * DDR Setup 49264eaa0eSValentin Longchamp */ 50264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 51264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 52264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 53264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 54264eaa0eSValentin Longchamp DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 55264eaa0eSValentin Longchamp 56264eaa0eSValentin Longchamp #define CFG_83XX_DDR_USES_CS0 57264eaa0eSValentin Longchamp 58264eaa0eSValentin Longchamp /* 59264eaa0eSValentin Longchamp * Manually set up DDR parameters 60264eaa0eSValentin Longchamp */ 61264eaa0eSValentin Longchamp #define CONFIG_DDR_II 62264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 63264eaa0eSValentin Longchamp 64264eaa0eSValentin Longchamp /* 65264eaa0eSValentin Longchamp * The reserved memory 66264eaa0eSValentin Longchamp */ 67264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 68264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BASE 0xF0000000 69264eaa0eSValentin Longchamp 70264eaa0eSValentin Longchamp #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 71264eaa0eSValentin Longchamp #define CONFIG_SYS_RAMBOOT 72264eaa0eSValentin Longchamp #endif 73264eaa0eSValentin Longchamp 74264eaa0eSValentin Longchamp /* Reserve 768 kB for Mon */ 75264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 76264eaa0eSValentin Longchamp 77264eaa0eSValentin Longchamp /* 78264eaa0eSValentin Longchamp * Initial RAM Base Address Setup 79264eaa0eSValentin Longchamp */ 80264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_LOCK 81264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 82264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 83264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 84264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 85264eaa0eSValentin Longchamp GENERATED_GBL_DATA_SIZE) 86264eaa0eSValentin Longchamp 87264eaa0eSValentin Longchamp /* 88264eaa0eSValentin Longchamp * Init Local Bus Memory Controller: 89264eaa0eSValentin Longchamp * 90264eaa0eSValentin Longchamp * Bank Bus Machine PortSz Size Device 91264eaa0eSValentin Longchamp * ---- --- ------- ------ ----- ------ 92264eaa0eSValentin Longchamp * 0 Local GPCM 16 bit 256MB FLASH 93264eaa0eSValentin Longchamp * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 94264eaa0eSValentin Longchamp * 95264eaa0eSValentin Longchamp */ 96264eaa0eSValentin Longchamp /* 97264eaa0eSValentin Longchamp * FLASH on the Local Bus 98264eaa0eSValentin Longchamp */ 99264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 100264eaa0eSValentin Longchamp #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 101264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 102264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_PROTECTION 103264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 104264eaa0eSValentin Longchamp 105264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 106264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ 107264eaa0eSValentin Longchamp 108264eaa0eSValentin Longchamp #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 109264eaa0eSValentin Longchamp (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 110264eaa0eSValentin Longchamp BR_V) 111264eaa0eSValentin Longchamp 112264eaa0eSValentin Longchamp #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 113264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 114264eaa0eSValentin Longchamp OR_GPCM_SCY_5 | \ 115264eaa0eSValentin Longchamp OR_GPCM_TRLX | OR_GPCM_EAD) 116264eaa0eSValentin Longchamp 117264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 118264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 119264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 120264eaa0eSValentin Longchamp 121264eaa0eSValentin Longchamp /* 122264eaa0eSValentin Longchamp * PRIO1/PIGGY on the local bus CS1 123264eaa0eSValentin Longchamp */ 124264eaa0eSValentin Longchamp /* Window base at flash base */ 125264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 126264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ 127264eaa0eSValentin Longchamp 128264eaa0eSValentin Longchamp #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 129264eaa0eSValentin Longchamp (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ 130264eaa0eSValentin Longchamp BR_V) 131264eaa0eSValentin Longchamp #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 132264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 133264eaa0eSValentin Longchamp OR_GPCM_SCY_2 | \ 134264eaa0eSValentin Longchamp OR_GPCM_TRLX | OR_GPCM_EAD) 135264eaa0eSValentin Longchamp 136264eaa0eSValentin Longchamp /* 137264eaa0eSValentin Longchamp * Serial Port 138264eaa0eSValentin Longchamp */ 139264eaa0eSValentin Longchamp #define CONFIG_CONS_INDEX 1 140264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550 141264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL 142264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE 1 143264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 144264eaa0eSValentin Longchamp 145264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 146264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 147264eaa0eSValentin Longchamp 148264eaa0eSValentin Longchamp /* Pass open firmware flat tree */ 149264eaa0eSValentin Longchamp #define CONFIG_OF_LIBFDT 150264eaa0eSValentin Longchamp #define CONFIG_OF_BOARD_SETUP 151264eaa0eSValentin Longchamp #define CONFIG_OF_STDOUT_VIA_ALIAS 152264eaa0eSValentin Longchamp 153264eaa0eSValentin Longchamp /* 154264eaa0eSValentin Longchamp * QE UEC ethernet configuration 155264eaa0eSValentin Longchamp */ 156264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH 157264eaa0eSValentin Longchamp #define CONFIG_ETHPRIME "UEC0" 158264eaa0eSValentin Longchamp 159264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH1 /* GETH1 */ 160264eaa0eSValentin Longchamp #define UEC_VERBOSE_DEBUG 1 161264eaa0eSValentin Longchamp 162264eaa0eSValentin Longchamp #ifdef CONFIG_UEC_ETH1 163264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 164264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 165264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 166264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 167264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_PHY_ADDR 0 168264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 169264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 170264eaa0eSValentin Longchamp #endif 171264eaa0eSValentin Longchamp 172264eaa0eSValentin Longchamp /* 173264eaa0eSValentin Longchamp * Environment 174264eaa0eSValentin Longchamp */ 175264eaa0eSValentin Longchamp 176264eaa0eSValentin Longchamp #ifndef CONFIG_SYS_RAMBOOT 177264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_IN_FLASH 178264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 179264eaa0eSValentin Longchamp CONFIG_SYS_MONITOR_LEN) 180264eaa0eSValentin Longchamp #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 181264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 182264eaa0eSValentin Longchamp 183264eaa0eSValentin Longchamp /* Address and size of Redundant Environment Sector */ 184264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 185264eaa0eSValentin Longchamp CONFIG_ENV_SECT_SIZE) 186264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 187264eaa0eSValentin Longchamp 188264eaa0eSValentin Longchamp #else /* CFG_SYS_RAMBOOT */ 189264eaa0eSValentin Longchamp #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 190264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 191264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 192264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE 0x2000 193264eaa0eSValentin Longchamp #endif /* CFG_SYS_RAMBOOT */ 194264eaa0eSValentin Longchamp 195264eaa0eSValentin Longchamp /* I2C */ 196264eaa0eSValentin Longchamp #define CONFIG_HARD_I2C /* I2C with hardware support */ 197264eaa0eSValentin Longchamp #define CONFIG_FSL_I2C 198264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ 199264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_SLAVE 0x7F 200264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_OFFSET 0x3000 201264eaa0eSValentin Longchamp 202264eaa0eSValentin Longchamp /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 203264eaa0eSValentin Longchamp #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 204264eaa0eSValentin Longchamp #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 205264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_MAX_TEMP 70 206264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_LOW_TEMP -30 207264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_HYSTERESIS 3 208264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) 209264eaa0eSValentin Longchamp 210264eaa0eSValentin Longchamp #if defined(CONFIG_CMD_NAND) 211264eaa0eSValentin Longchamp #define CONFIG_NAND_KMETER1 212264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE 1 213264eaa0eSValentin Longchamp #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 214264eaa0eSValentin Longchamp #endif 215264eaa0eSValentin Longchamp 216264eaa0eSValentin Longchamp #if defined(CONFIG_PCI) 217264eaa0eSValentin Longchamp #define CONFIG_CMD_PCI 218264eaa0eSValentin Longchamp #endif 219264eaa0eSValentin Longchamp 220264eaa0eSValentin Longchamp /* 221264eaa0eSValentin Longchamp * For booting Linux, the board info and command line data 222264eaa0eSValentin Longchamp * have to be in the first 8 MB of memory, since this is 223264eaa0eSValentin Longchamp * the maximum mapped by the Linux kernel during initialization. 224264eaa0eSValentin Longchamp */ 225264eaa0eSValentin Longchamp #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 226264eaa0eSValentin Longchamp 227264eaa0eSValentin Longchamp /* 228264eaa0eSValentin Longchamp * Core HID Setup 229264eaa0eSValentin Longchamp */ 230264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_INIT 0x000000000 231264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 232264eaa0eSValentin Longchamp HID0_ENABLE_INSTRUCTION_CACHE) 233264eaa0eSValentin Longchamp #define CONFIG_SYS_HID2 HID2_HBE 234264eaa0eSValentin Longchamp 235264eaa0eSValentin Longchamp /* 236264eaa0eSValentin Longchamp * MMU Setup 237264eaa0eSValentin Longchamp */ 238264eaa0eSValentin Longchamp 239264eaa0eSValentin Longchamp #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 240264eaa0eSValentin Longchamp 241264eaa0eSValentin Longchamp /* DDR: cache cacheable */ 242*72cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 243264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 244264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 245264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 246264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 247264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 248264eaa0eSValentin Longchamp 249264eaa0eSValentin Longchamp /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 250*72cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 251264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 252264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 253264eaa0eSValentin Longchamp | BATU_VP) 254264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 255264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 256264eaa0eSValentin Longchamp 257264eaa0eSValentin Longchamp /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 258*72cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 259264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 260264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 261264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 262*72cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 263264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 264264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 265264eaa0eSValentin Longchamp 266264eaa0eSValentin Longchamp /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 267*72cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 268264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 269264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 270264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 271*72cd4087SJoe Hershberger #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 272264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 273264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 274264eaa0eSValentin Longchamp 275264eaa0eSValentin Longchamp /* Stack in dcache: cacheable, no memory coherence */ 276*72cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 277264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 278264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 279264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 280264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 281264eaa0eSValentin Longchamp 282264eaa0eSValentin Longchamp /* 283264eaa0eSValentin Longchamp * Internal Definitions 284264eaa0eSValentin Longchamp */ 285264eaa0eSValentin Longchamp #define BOOTFLASH_START 0xF0000000 286264eaa0eSValentin Longchamp 287264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY "ttyS0" 288264eaa0eSValentin Longchamp 289264eaa0eSValentin Longchamp /* 290264eaa0eSValentin Longchamp * Environment Configuration 291264eaa0eSValentin Longchamp */ 292264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE 293264eaa0eSValentin Longchamp #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 294264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV "km-common=empty\0" 295264eaa0eSValentin Longchamp #endif 296264eaa0eSValentin Longchamp 297b648bfc2SHolger Brunck #ifndef CONFIG_KM_DEF_ARCH 298b648bfc2SHolger Brunck #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 299264eaa0eSValentin Longchamp #endif 300264eaa0eSValentin Longchamp 301264eaa0eSValentin Longchamp #define CONFIG_EXTRA_ENV_SETTINGS \ 302264eaa0eSValentin Longchamp CONFIG_KM_DEF_ENV \ 303b648bfc2SHolger Brunck CONFIG_KM_DEF_ARCH \ 304264eaa0eSValentin Longchamp "dtt_bus=pca9547:70:a\0" \ 305264eaa0eSValentin Longchamp "EEprom_ivm=pca9547:70:9\0" \ 306264eaa0eSValentin Longchamp "newenv=" \ 307264eaa0eSValentin Longchamp "prot off 0xF00C0000 +0x40000 && " \ 308264eaa0eSValentin Longchamp "era 0xF00C0000 +0x40000\0" \ 309264eaa0eSValentin Longchamp "unlock=yes\0" \ 310264eaa0eSValentin Longchamp "" 311264eaa0eSValentin Longchamp 312264eaa0eSValentin Longchamp #if defined(CONFIG_UEC_ETH) 313264eaa0eSValentin Longchamp #define CONFIG_HAS_ETH0 314264eaa0eSValentin Longchamp #endif 315264eaa0eSValentin Longchamp 316264eaa0eSValentin Longchamp #endif /* __CONFIG_KM83XX_H */ 317