1264eaa0eSValentin Longchamp /* 2264eaa0eSValentin Longchamp * (C) Copyright 2010 3264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4264eaa0eSValentin Longchamp * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6264eaa0eSValentin Longchamp */ 7264eaa0eSValentin Longchamp 8264eaa0eSValentin Longchamp #ifndef __CONFIG_KM83XX_H 9264eaa0eSValentin Longchamp #define __CONFIG_KM83XX_H 10264eaa0eSValentin Longchamp 11a0744285SValentin Longchamp #define CONFIG_DISPLAY_BOARDINFO 12a0744285SValentin Longchamp 13264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */ 14264eaa0eSValentin Longchamp #include "keymile-common.h" 15264eaa0eSValentin Longchamp #include "km-powerpc.h" 16264eaa0eSValentin Longchamp 17cf73639dSAndreas Huber #ifndef MTDIDS_DEFAULT 18264eaa0eSValentin Longchamp # define MTDIDS_DEFAULT "nor0=boot" 19cf73639dSAndreas Huber #endif /* MTDIDS_DEFAULT */ 20cf73639dSAndreas Huber 21cf73639dSAndreas Huber #ifndef MTDPARTS_DEFAULT 22264eaa0eSValentin Longchamp # define MTDPARTS_DEFAULT "mtdparts=" \ 23264eaa0eSValentin Longchamp "boot:" \ 24264eaa0eSValentin Longchamp "768k(u-boot)," \ 25264eaa0eSValentin Longchamp "128k(env)," \ 26264eaa0eSValentin Longchamp "128k(envred)," \ 27cf73639dSAndreas Huber "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 28cf73639dSAndreas Huber #endif /* MTDPARTS_DEFAULT */ 29264eaa0eSValentin Longchamp 30264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R 31264eaa0eSValentin Longchamp /* 32264eaa0eSValentin Longchamp * System Clock Setup 33264eaa0eSValentin Longchamp */ 34264eaa0eSValentin Longchamp #define CONFIG_83XX_CLKIN 66000000 35264eaa0eSValentin Longchamp #define CONFIG_SYS_CLK_FREQ 66000000 36264eaa0eSValentin Longchamp #define CONFIG_83XX_PCICLK 66000000 37264eaa0eSValentin Longchamp 38264eaa0eSValentin Longchamp /* 39264eaa0eSValentin Longchamp * IMMR new address 40264eaa0eSValentin Longchamp */ 41264eaa0eSValentin Longchamp #define CONFIG_SYS_IMMR 0xE0000000 42264eaa0eSValentin Longchamp 43264eaa0eSValentin Longchamp /* 44264eaa0eSValentin Longchamp * Bus Arbitration Configuration Register (ACR) 45264eaa0eSValentin Longchamp */ 46264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 47264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 48264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 49264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 50264eaa0eSValentin Longchamp 51264eaa0eSValentin Longchamp /* 52264eaa0eSValentin Longchamp * DDR Setup 53264eaa0eSValentin Longchamp */ 54264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 55264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 560f2b721cSHolger Brunck #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 570f2b721cSHolger Brunck 58264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 59264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 60264eaa0eSValentin Longchamp DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 61264eaa0eSValentin Longchamp 62264eaa0eSValentin Longchamp #define CFG_83XX_DDR_USES_CS0 63264eaa0eSValentin Longchamp 64264eaa0eSValentin Longchamp /* 65264eaa0eSValentin Longchamp * Manually set up DDR parameters 66264eaa0eSValentin Longchamp */ 67264eaa0eSValentin Longchamp #define CONFIG_DDR_II 68264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 69264eaa0eSValentin Longchamp 70264eaa0eSValentin Longchamp /* 71264eaa0eSValentin Longchamp * The reserved memory 72264eaa0eSValentin Longchamp */ 73264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 74264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BASE 0xF0000000 75264eaa0eSValentin Longchamp 76264eaa0eSValentin Longchamp #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 77264eaa0eSValentin Longchamp #define CONFIG_SYS_RAMBOOT 78264eaa0eSValentin Longchamp #endif 79264eaa0eSValentin Longchamp 80264eaa0eSValentin Longchamp /* Reserve 768 kB for Mon */ 81264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 82264eaa0eSValentin Longchamp 83264eaa0eSValentin Longchamp /* 84264eaa0eSValentin Longchamp * Initial RAM Base Address Setup 85264eaa0eSValentin Longchamp */ 86264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_LOCK 87264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 88264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 89264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 90264eaa0eSValentin Longchamp GENERATED_GBL_DATA_SIZE) 91264eaa0eSValentin Longchamp 92264eaa0eSValentin Longchamp /* 93264eaa0eSValentin Longchamp * Init Local Bus Memory Controller: 94264eaa0eSValentin Longchamp * 95264eaa0eSValentin Longchamp * Bank Bus Machine PortSz Size Device 96264eaa0eSValentin Longchamp * ---- --- ------- ------ ----- ------ 97264eaa0eSValentin Longchamp * 0 Local GPCM 16 bit 256MB FLASH 98264eaa0eSValentin Longchamp * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 99264eaa0eSValentin Longchamp * 100264eaa0eSValentin Longchamp */ 101264eaa0eSValentin Longchamp /* 102264eaa0eSValentin Longchamp * FLASH on the Local Bus 103264eaa0eSValentin Longchamp */ 104264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 105264eaa0eSValentin Longchamp #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 106264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 107264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_PROTECTION 108264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 109264eaa0eSValentin Longchamp 110264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1117d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 112264eaa0eSValentin Longchamp 113264eaa0eSValentin Longchamp #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1147d6a0982SJoe Hershberger BR_PS_16 | /* 16 bit port size */ \ 1157d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 116264eaa0eSValentin Longchamp BR_V) 117264eaa0eSValentin Longchamp 118264eaa0eSValentin Longchamp #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 119264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 120264eaa0eSValentin Longchamp OR_GPCM_SCY_5 | \ 1217d6a0982SJoe Hershberger OR_GPCM_TRLX_SET | OR_GPCM_EAD) 122264eaa0eSValentin Longchamp 123264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 124264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 125264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 126264eaa0eSValentin Longchamp 127264eaa0eSValentin Longchamp /* 128264eaa0eSValentin Longchamp * PRIO1/PIGGY on the local bus CS1 129264eaa0eSValentin Longchamp */ 130264eaa0eSValentin Longchamp /* Window base at flash base */ 131264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 1327d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 133264eaa0eSValentin Longchamp 134264eaa0eSValentin Longchamp #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 1357d6a0982SJoe Hershberger BR_PS_8 | /* 8 bit port size */ \ 1367d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 137264eaa0eSValentin Longchamp BR_V) 138264eaa0eSValentin Longchamp #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 139264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 140264eaa0eSValentin Longchamp OR_GPCM_SCY_2 | \ 1417d6a0982SJoe Hershberger OR_GPCM_TRLX_SET | OR_GPCM_EAD) 142264eaa0eSValentin Longchamp 143264eaa0eSValentin Longchamp /* 144264eaa0eSValentin Longchamp * Serial Port 145264eaa0eSValentin Longchamp */ 146264eaa0eSValentin Longchamp #define CONFIG_CONS_INDEX 1 147264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550 148264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL 149264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE 1 150264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 151264eaa0eSValentin Longchamp 152264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 153264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 154264eaa0eSValentin Longchamp 155264eaa0eSValentin Longchamp #define CONFIG_OF_STDOUT_VIA_ALIAS 156264eaa0eSValentin Longchamp 157264eaa0eSValentin Longchamp /* 158264eaa0eSValentin Longchamp * QE UEC ethernet configuration 159264eaa0eSValentin Longchamp */ 160264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH 161264eaa0eSValentin Longchamp #define CONFIG_ETHPRIME "UEC0" 162264eaa0eSValentin Longchamp 1635bcd64cfSKarlheinz Jerg #if !defined(CONFIG_MPC8309) 164264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH1 /* GETH1 */ 165264eaa0eSValentin Longchamp #define UEC_VERBOSE_DEBUG 1 1665bcd64cfSKarlheinz Jerg #endif 167264eaa0eSValentin Longchamp 168264eaa0eSValentin Longchamp #ifdef CONFIG_UEC_ETH1 169264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 170264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 171264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 172264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 173264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_PHY_ADDR 0 174264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 175264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 176264eaa0eSValentin Longchamp #endif 177264eaa0eSValentin Longchamp 178264eaa0eSValentin Longchamp /* 179264eaa0eSValentin Longchamp * Environment 180264eaa0eSValentin Longchamp */ 181264eaa0eSValentin Longchamp 182264eaa0eSValentin Longchamp #ifndef CONFIG_SYS_RAMBOOT 183264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_IN_FLASH 184*68005ea6SValentin Longchamp #ifndef CONFIG_ENV_ADDR 185264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 186264eaa0eSValentin Longchamp CONFIG_SYS_MONITOR_LEN) 187*68005ea6SValentin Longchamp #endif 188264eaa0eSValentin Longchamp #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 189*68005ea6SValentin Longchamp #ifndef CONFIG_ENV_OFFSET 190264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 191*68005ea6SValentin Longchamp #endif 192264eaa0eSValentin Longchamp 193264eaa0eSValentin Longchamp /* Address and size of Redundant Environment Sector */ 194264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 195264eaa0eSValentin Longchamp CONFIG_ENV_SECT_SIZE) 196264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 197264eaa0eSValentin Longchamp 198264eaa0eSValentin Longchamp #else /* CFG_SYS_RAMBOOT */ 199264eaa0eSValentin Longchamp #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 200264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 201264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 202264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE 0x2000 203264eaa0eSValentin Longchamp #endif /* CFG_SYS_RAMBOOT */ 204264eaa0eSValentin Longchamp 205264eaa0eSValentin Longchamp /* I2C */ 20600f792e0SHeiko Schocher #define CONFIG_SYS_I2C 20700f792e0SHeiko Schocher #define CONFIG_SYS_NUM_I2C_BUSES 4 20800f792e0SHeiko Schocher #define CONFIG_SYS_I2C_MAX_HOPS 1 20900f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 21000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 200000 21100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 21200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 213264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_OFFSET 0x3000 21400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 200000 21500f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 21600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 21700f792e0SHeiko Schocher #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ 21800f792e0SHeiko Schocher {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ 21900f792e0SHeiko Schocher {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ 22000f792e0SHeiko Schocher {1, {I2C_NULL_HOP} } } 221264eaa0eSValentin Longchamp 222f3e93617SHeiko Schocher #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ 223264eaa0eSValentin Longchamp 224264eaa0eSValentin Longchamp /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 225264eaa0eSValentin Longchamp #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 226264eaa0eSValentin Longchamp #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 227264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_MAX_TEMP 70 228264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_HYSTERESIS 3 22900f792e0SHeiko Schocher #define CONFIG_SYS_DTT_BUS_NUM 1 230264eaa0eSValentin Longchamp 231264eaa0eSValentin Longchamp #if defined(CONFIG_CMD_NAND) 232264eaa0eSValentin Longchamp #define CONFIG_NAND_KMETER1 233264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE 1 234264eaa0eSValentin Longchamp #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 235264eaa0eSValentin Longchamp #endif 236264eaa0eSValentin Longchamp 237264eaa0eSValentin Longchamp #if defined(CONFIG_PCI) 238264eaa0eSValentin Longchamp #define CONFIG_CMD_PCI 239264eaa0eSValentin Longchamp #endif 240264eaa0eSValentin Longchamp 241264eaa0eSValentin Longchamp /* 242264eaa0eSValentin Longchamp * For booting Linux, the board info and command line data 243264eaa0eSValentin Longchamp * have to be in the first 8 MB of memory, since this is 244264eaa0eSValentin Longchamp * the maximum mapped by the Linux kernel during initialization. 245264eaa0eSValentin Longchamp */ 246264eaa0eSValentin Longchamp #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 247264eaa0eSValentin Longchamp 248264eaa0eSValentin Longchamp /* 249264eaa0eSValentin Longchamp * Core HID Setup 250264eaa0eSValentin Longchamp */ 251264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_INIT 0x000000000 252264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 253264eaa0eSValentin Longchamp HID0_ENABLE_INSTRUCTION_CACHE) 254264eaa0eSValentin Longchamp #define CONFIG_SYS_HID2 HID2_HBE 255264eaa0eSValentin Longchamp 256264eaa0eSValentin Longchamp /* 257264eaa0eSValentin Longchamp * MMU Setup 258264eaa0eSValentin Longchamp */ 259264eaa0eSValentin Longchamp 260264eaa0eSValentin Longchamp #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 261264eaa0eSValentin Longchamp 262264eaa0eSValentin Longchamp /* DDR: cache cacheable */ 26372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 264264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 265264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 266264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 267264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 268264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 269264eaa0eSValentin Longchamp 270264eaa0eSValentin Longchamp /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 27172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 272264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 273264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 274264eaa0eSValentin Longchamp | BATU_VP) 275264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 276264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 277264eaa0eSValentin Longchamp 278264eaa0eSValentin Longchamp /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 27972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 280264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 281264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 282264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 28372cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 284264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 285264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 286264eaa0eSValentin Longchamp 287264eaa0eSValentin Longchamp /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 28872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 289264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 290264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 291264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 29272cd4087SJoe Hershberger #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 293264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 294264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 295264eaa0eSValentin Longchamp 296264eaa0eSValentin Longchamp /* Stack in dcache: cacheable, no memory coherence */ 29772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 298264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 299264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 300264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 301264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 302264eaa0eSValentin Longchamp 303264eaa0eSValentin Longchamp /* 304264eaa0eSValentin Longchamp * Internal Definitions 305264eaa0eSValentin Longchamp */ 306264eaa0eSValentin Longchamp #define BOOTFLASH_START 0xF0000000 307264eaa0eSValentin Longchamp 308264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY "ttyS0" 309264eaa0eSValentin Longchamp 310264eaa0eSValentin Longchamp /* 311264eaa0eSValentin Longchamp * Environment Configuration 312264eaa0eSValentin Longchamp */ 313264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE 314264eaa0eSValentin Longchamp #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 315264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV "km-common=empty\0" 316264eaa0eSValentin Longchamp #endif 317264eaa0eSValentin Longchamp 318b648bfc2SHolger Brunck #ifndef CONFIG_KM_DEF_ARCH 319b648bfc2SHolger Brunck #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 320264eaa0eSValentin Longchamp #endif 321264eaa0eSValentin Longchamp 322264eaa0eSValentin Longchamp #define CONFIG_EXTRA_ENV_SETTINGS \ 323264eaa0eSValentin Longchamp CONFIG_KM_DEF_ENV \ 324b648bfc2SHolger Brunck CONFIG_KM_DEF_ARCH \ 325264eaa0eSValentin Longchamp "newenv=" \ 326*68005ea6SValentin Longchamp "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \ 327*68005ea6SValentin Longchamp "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \ 328264eaa0eSValentin Longchamp "unlock=yes\0" \ 329264eaa0eSValentin Longchamp "" 330264eaa0eSValentin Longchamp 331264eaa0eSValentin Longchamp #if defined(CONFIG_UEC_ETH) 332264eaa0eSValentin Longchamp #define CONFIG_HAS_ETH0 333264eaa0eSValentin Longchamp #endif 334264eaa0eSValentin Longchamp 335264eaa0eSValentin Longchamp #endif /* __CONFIG_KM83XX_H */ 336