1264eaa0eSValentin Longchamp /* 2264eaa0eSValentin Longchamp * (C) Copyright 2010 3264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4264eaa0eSValentin Longchamp * 5264eaa0eSValentin Longchamp * This program is free software; you can redistribute it and/or 6264eaa0eSValentin Longchamp * modify it under the terms of the GNU General Public License as 7264eaa0eSValentin Longchamp * published by the Free Software Foundation; either version 2 of 8264eaa0eSValentin Longchamp * the License, or (at your option) any later version. 9264eaa0eSValentin Longchamp */ 10264eaa0eSValentin Longchamp 11264eaa0eSValentin Longchamp #ifndef __CONFIG_KM83XX_H 12264eaa0eSValentin Longchamp #define __CONFIG_KM83XX_H 13264eaa0eSValentin Longchamp 14264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */ 15264eaa0eSValentin Longchamp #include "keymile-common.h" 16264eaa0eSValentin Longchamp #include "km-powerpc.h" 17264eaa0eSValentin Longchamp 18cf73639dSAndreas Huber #ifndef MTDIDS_DEFAULT 19264eaa0eSValentin Longchamp # define MTDIDS_DEFAULT "nor0=boot" 20cf73639dSAndreas Huber #endif /* MTDIDS_DEFAULT */ 21cf73639dSAndreas Huber 22cf73639dSAndreas Huber #ifndef MTDPARTS_DEFAULT 23264eaa0eSValentin Longchamp # define MTDPARTS_DEFAULT "mtdparts=" \ 24264eaa0eSValentin Longchamp "boot:" \ 25264eaa0eSValentin Longchamp "768k(u-boot)," \ 26264eaa0eSValentin Longchamp "128k(env)," \ 27264eaa0eSValentin Longchamp "128k(envred)," \ 28cf73639dSAndreas Huber "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" 29cf73639dSAndreas Huber #endif /* MTDPARTS_DEFAULT */ 30264eaa0eSValentin Longchamp 31264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R 32264eaa0eSValentin Longchamp /* 33264eaa0eSValentin Longchamp * System Clock Setup 34264eaa0eSValentin Longchamp */ 35264eaa0eSValentin Longchamp #define CONFIG_83XX_CLKIN 66000000 36264eaa0eSValentin Longchamp #define CONFIG_SYS_CLK_FREQ 66000000 37264eaa0eSValentin Longchamp #define CONFIG_83XX_PCICLK 66000000 38264eaa0eSValentin Longchamp 39264eaa0eSValentin Longchamp /* 40264eaa0eSValentin Longchamp * IMMR new address 41264eaa0eSValentin Longchamp */ 42264eaa0eSValentin Longchamp #define CONFIG_SYS_IMMR 0xE0000000 43264eaa0eSValentin Longchamp 44264eaa0eSValentin Longchamp /* 45264eaa0eSValentin Longchamp * Bus Arbitration Configuration Register (ACR) 46264eaa0eSValentin Longchamp */ 47264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 48264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 49264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 50264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 51264eaa0eSValentin Longchamp 52264eaa0eSValentin Longchamp /* 53264eaa0eSValentin Longchamp * DDR Setup 54264eaa0eSValentin Longchamp */ 55264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 56264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 570f2b721cSHolger Brunck #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ 580f2b721cSHolger Brunck 59264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 60264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 61264eaa0eSValentin Longchamp DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 62264eaa0eSValentin Longchamp 63264eaa0eSValentin Longchamp #define CFG_83XX_DDR_USES_CS0 64264eaa0eSValentin Longchamp 65264eaa0eSValentin Longchamp /* 66264eaa0eSValentin Longchamp * Manually set up DDR parameters 67264eaa0eSValentin Longchamp */ 68264eaa0eSValentin Longchamp #define CONFIG_DDR_II 69264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 70264eaa0eSValentin Longchamp 71264eaa0eSValentin Longchamp /* 72264eaa0eSValentin Longchamp * The reserved memory 73264eaa0eSValentin Longchamp */ 74264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BASE 0xF0000000 76264eaa0eSValentin Longchamp 77264eaa0eSValentin Longchamp #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 78264eaa0eSValentin Longchamp #define CONFIG_SYS_RAMBOOT 79264eaa0eSValentin Longchamp #endif 80264eaa0eSValentin Longchamp 81264eaa0eSValentin Longchamp /* Reserve 768 kB for Mon */ 82264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 83264eaa0eSValentin Longchamp 84264eaa0eSValentin Longchamp /* 85264eaa0eSValentin Longchamp * Initial RAM Base Address Setup 86264eaa0eSValentin Longchamp */ 87264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_LOCK 88264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 89264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 90264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 91264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 92264eaa0eSValentin Longchamp GENERATED_GBL_DATA_SIZE) 93264eaa0eSValentin Longchamp 94264eaa0eSValentin Longchamp /* 95264eaa0eSValentin Longchamp * Init Local Bus Memory Controller: 96264eaa0eSValentin Longchamp * 97264eaa0eSValentin Longchamp * Bank Bus Machine PortSz Size Device 98264eaa0eSValentin Longchamp * ---- --- ------- ------ ----- ------ 99264eaa0eSValentin Longchamp * 0 Local GPCM 16 bit 256MB FLASH 100264eaa0eSValentin Longchamp * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 101264eaa0eSValentin Longchamp * 102264eaa0eSValentin Longchamp */ 103264eaa0eSValentin Longchamp /* 104264eaa0eSValentin Longchamp * FLASH on the Local Bus 105264eaa0eSValentin Longchamp */ 106264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 107264eaa0eSValentin Longchamp #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 108264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 109264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_PROTECTION 110264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 111264eaa0eSValentin Longchamp 112264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1137d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 114264eaa0eSValentin Longchamp 115264eaa0eSValentin Longchamp #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1167d6a0982SJoe Hershberger BR_PS_16 | /* 16 bit port size */ \ 1177d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 118264eaa0eSValentin Longchamp BR_V) 119264eaa0eSValentin Longchamp 120264eaa0eSValentin Longchamp #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 121264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 122264eaa0eSValentin Longchamp OR_GPCM_SCY_5 | \ 1237d6a0982SJoe Hershberger OR_GPCM_TRLX_SET | OR_GPCM_EAD) 124264eaa0eSValentin Longchamp 125264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 126264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 127264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 128264eaa0eSValentin Longchamp 129264eaa0eSValentin Longchamp /* 130264eaa0eSValentin Longchamp * PRIO1/PIGGY on the local bus CS1 131264eaa0eSValentin Longchamp */ 132264eaa0eSValentin Longchamp /* Window base at flash base */ 133264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 1347d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 135264eaa0eSValentin Longchamp 136264eaa0eSValentin Longchamp #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 1377d6a0982SJoe Hershberger BR_PS_8 | /* 8 bit port size */ \ 1387d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 139264eaa0eSValentin Longchamp BR_V) 140264eaa0eSValentin Longchamp #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 141264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 142264eaa0eSValentin Longchamp OR_GPCM_SCY_2 | \ 1437d6a0982SJoe Hershberger OR_GPCM_TRLX_SET | OR_GPCM_EAD) 144264eaa0eSValentin Longchamp 145264eaa0eSValentin Longchamp /* 146264eaa0eSValentin Longchamp * Serial Port 147264eaa0eSValentin Longchamp */ 148264eaa0eSValentin Longchamp #define CONFIG_CONS_INDEX 1 149264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550 150264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL 151264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE 1 152264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 153264eaa0eSValentin Longchamp 154264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 155264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 156264eaa0eSValentin Longchamp 157264eaa0eSValentin Longchamp /* Pass open firmware flat tree */ 158264eaa0eSValentin Longchamp #define CONFIG_OF_LIBFDT 159264eaa0eSValentin Longchamp #define CONFIG_OF_BOARD_SETUP 160264eaa0eSValentin Longchamp #define CONFIG_OF_STDOUT_VIA_ALIAS 161264eaa0eSValentin Longchamp 162264eaa0eSValentin Longchamp /* 163264eaa0eSValentin Longchamp * QE UEC ethernet configuration 164264eaa0eSValentin Longchamp */ 165264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH 166264eaa0eSValentin Longchamp #define CONFIG_ETHPRIME "UEC0" 167264eaa0eSValentin Longchamp 168*5bcd64cfSKarlheinz Jerg #if !defined(CONFIG_MPC8309) 169264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH1 /* GETH1 */ 170264eaa0eSValentin Longchamp #define UEC_VERBOSE_DEBUG 1 171*5bcd64cfSKarlheinz Jerg #endif 172264eaa0eSValentin Longchamp 173264eaa0eSValentin Longchamp #ifdef CONFIG_UEC_ETH1 174264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 175264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 176264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 177264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 178264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_PHY_ADDR 0 179264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 180264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 181264eaa0eSValentin Longchamp #endif 182264eaa0eSValentin Longchamp 183264eaa0eSValentin Longchamp /* 184264eaa0eSValentin Longchamp * Environment 185264eaa0eSValentin Longchamp */ 186264eaa0eSValentin Longchamp 187264eaa0eSValentin Longchamp #ifndef CONFIG_SYS_RAMBOOT 188264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_IN_FLASH 189264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 190264eaa0eSValentin Longchamp CONFIG_SYS_MONITOR_LEN) 191264eaa0eSValentin Longchamp #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 192264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 193264eaa0eSValentin Longchamp 194264eaa0eSValentin Longchamp /* Address and size of Redundant Environment Sector */ 195264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 196264eaa0eSValentin Longchamp CONFIG_ENV_SECT_SIZE) 197264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 198264eaa0eSValentin Longchamp 199264eaa0eSValentin Longchamp #else /* CFG_SYS_RAMBOOT */ 200264eaa0eSValentin Longchamp #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 201264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 202264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 203264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE 0x2000 204264eaa0eSValentin Longchamp #endif /* CFG_SYS_RAMBOOT */ 205264eaa0eSValentin Longchamp 206264eaa0eSValentin Longchamp /* I2C */ 207264eaa0eSValentin Longchamp #define CONFIG_HARD_I2C /* I2C with hardware support */ 208264eaa0eSValentin Longchamp #define CONFIG_FSL_I2C 209264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ 210264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_SLAVE 0x7F 211264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_OFFSET 0x3000 212264eaa0eSValentin Longchamp 213264eaa0eSValentin Longchamp /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 214264eaa0eSValentin Longchamp #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 215264eaa0eSValentin Longchamp #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 216264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_MAX_TEMP 70 217264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_LOW_TEMP -30 218264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_HYSTERESIS 3 219264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) 220264eaa0eSValentin Longchamp 221264eaa0eSValentin Longchamp #if defined(CONFIG_CMD_NAND) 222264eaa0eSValentin Longchamp #define CONFIG_NAND_KMETER1 223264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE 1 224264eaa0eSValentin Longchamp #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 225264eaa0eSValentin Longchamp #endif 226264eaa0eSValentin Longchamp 227264eaa0eSValentin Longchamp #if defined(CONFIG_PCI) 228264eaa0eSValentin Longchamp #define CONFIG_CMD_PCI 229264eaa0eSValentin Longchamp #endif 230264eaa0eSValentin Longchamp 231264eaa0eSValentin Longchamp /* 232264eaa0eSValentin Longchamp * For booting Linux, the board info and command line data 233264eaa0eSValentin Longchamp * have to be in the first 8 MB of memory, since this is 234264eaa0eSValentin Longchamp * the maximum mapped by the Linux kernel during initialization. 235264eaa0eSValentin Longchamp */ 236264eaa0eSValentin Longchamp #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 237264eaa0eSValentin Longchamp 238264eaa0eSValentin Longchamp /* 239264eaa0eSValentin Longchamp * Core HID Setup 240264eaa0eSValentin Longchamp */ 241264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_INIT 0x000000000 242264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 243264eaa0eSValentin Longchamp HID0_ENABLE_INSTRUCTION_CACHE) 244264eaa0eSValentin Longchamp #define CONFIG_SYS_HID2 HID2_HBE 245264eaa0eSValentin Longchamp 246264eaa0eSValentin Longchamp /* 247264eaa0eSValentin Longchamp * MMU Setup 248264eaa0eSValentin Longchamp */ 249264eaa0eSValentin Longchamp 250264eaa0eSValentin Longchamp #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 251264eaa0eSValentin Longchamp 252264eaa0eSValentin Longchamp /* DDR: cache cacheable */ 25372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 254264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 255264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 256264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 257264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 258264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 259264eaa0eSValentin Longchamp 260264eaa0eSValentin Longchamp /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 26172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 262264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 263264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 264264eaa0eSValentin Longchamp | BATU_VP) 265264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 266264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 267264eaa0eSValentin Longchamp 268264eaa0eSValentin Longchamp /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 26972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 270264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 271264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 272264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 27372cd4087SJoe Hershberger #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ 274264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 275264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 276264eaa0eSValentin Longchamp 277264eaa0eSValentin Longchamp /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 27872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 279264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 280264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 281264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 28272cd4087SJoe Hershberger #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 283264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 284264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 285264eaa0eSValentin Longchamp 286264eaa0eSValentin Longchamp /* Stack in dcache: cacheable, no memory coherence */ 28772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 288264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 289264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 290264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 291264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 292264eaa0eSValentin Longchamp 293264eaa0eSValentin Longchamp /* 294264eaa0eSValentin Longchamp * Internal Definitions 295264eaa0eSValentin Longchamp */ 296264eaa0eSValentin Longchamp #define BOOTFLASH_START 0xF0000000 297264eaa0eSValentin Longchamp 298264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY "ttyS0" 299264eaa0eSValentin Longchamp 300264eaa0eSValentin Longchamp /* 301264eaa0eSValentin Longchamp * Environment Configuration 302264eaa0eSValentin Longchamp */ 303264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE 304264eaa0eSValentin Longchamp #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 305264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV "km-common=empty\0" 306264eaa0eSValentin Longchamp #endif 307264eaa0eSValentin Longchamp 308b648bfc2SHolger Brunck #ifndef CONFIG_KM_DEF_ARCH 309b648bfc2SHolger Brunck #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 310264eaa0eSValentin Longchamp #endif 311264eaa0eSValentin Longchamp 312264eaa0eSValentin Longchamp #define CONFIG_EXTRA_ENV_SETTINGS \ 313264eaa0eSValentin Longchamp CONFIG_KM_DEF_ENV \ 314b648bfc2SHolger Brunck CONFIG_KM_DEF_ARCH \ 315264eaa0eSValentin Longchamp "dtt_bus=pca9547:70:a\0" \ 316264eaa0eSValentin Longchamp "EEprom_ivm=pca9547:70:9\0" \ 317264eaa0eSValentin Longchamp "newenv=" \ 318264eaa0eSValentin Longchamp "prot off 0xF00C0000 +0x40000 && " \ 319264eaa0eSValentin Longchamp "era 0xF00C0000 +0x40000\0" \ 320264eaa0eSValentin Longchamp "unlock=yes\0" \ 321264eaa0eSValentin Longchamp "" 322264eaa0eSValentin Longchamp 323264eaa0eSValentin Longchamp #if defined(CONFIG_UEC_ETH) 324264eaa0eSValentin Longchamp #define CONFIG_HAS_ETH0 325264eaa0eSValentin Longchamp #endif 326264eaa0eSValentin Longchamp 327264eaa0eSValentin Longchamp #endif /* __CONFIG_KM83XX_H */ 328