1*264eaa0eSValentin Longchamp /* 2*264eaa0eSValentin Longchamp * (C) Copyright 2010 3*264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4*264eaa0eSValentin Longchamp * 5*264eaa0eSValentin Longchamp * This program is free software; you can redistribute it and/or 6*264eaa0eSValentin Longchamp * modify it under the terms of the GNU General Public License as 7*264eaa0eSValentin Longchamp * published by the Free Software Foundation; either version 2 of 8*264eaa0eSValentin Longchamp * the License, or (at your option) any later version. 9*264eaa0eSValentin Longchamp */ 10*264eaa0eSValentin Longchamp 11*264eaa0eSValentin Longchamp #ifndef __CONFIG_KM83XX_H 12*264eaa0eSValentin Longchamp #define __CONFIG_KM83XX_H 13*264eaa0eSValentin Longchamp 14*264eaa0eSValentin Longchamp /* include common defines/options for all Keymile boards */ 15*264eaa0eSValentin Longchamp #include "keymile-common.h" 16*264eaa0eSValentin Longchamp #include "km-powerpc.h" 17*264eaa0eSValentin Longchamp 18*264eaa0eSValentin Longchamp #define MTDIDS_DEFAULT "nor0=boot" 19*264eaa0eSValentin Longchamp #define MTDPARTS_DEFAULT "mtdparts=" \ 20*264eaa0eSValentin Longchamp "boot:" \ 21*264eaa0eSValentin Longchamp "768k(u-boot)," \ 22*264eaa0eSValentin Longchamp "128k(env)," \ 23*264eaa0eSValentin Longchamp "128k(envred)," \ 24*264eaa0eSValentin Longchamp "-(" CONFIG_KM_UBI_PARTITION_NAME ")" 25*264eaa0eSValentin Longchamp 26*264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R 27*264eaa0eSValentin Longchamp /* 28*264eaa0eSValentin Longchamp * System Clock Setup 29*264eaa0eSValentin Longchamp */ 30*264eaa0eSValentin Longchamp #define CONFIG_83XX_CLKIN 66000000 31*264eaa0eSValentin Longchamp #define CONFIG_SYS_CLK_FREQ 66000000 32*264eaa0eSValentin Longchamp #define CONFIG_83XX_PCICLK 66000000 33*264eaa0eSValentin Longchamp 34*264eaa0eSValentin Longchamp /* 35*264eaa0eSValentin Longchamp * IMMR new address 36*264eaa0eSValentin Longchamp */ 37*264eaa0eSValentin Longchamp #define CONFIG_SYS_IMMR 0xE0000000 38*264eaa0eSValentin Longchamp 39*264eaa0eSValentin Longchamp /* 40*264eaa0eSValentin Longchamp * Bus Arbitration Configuration Register (ACR) 41*264eaa0eSValentin Longchamp */ 42*264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ 43*264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ 44*264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ 45*264eaa0eSValentin Longchamp #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ 46*264eaa0eSValentin Longchamp 47*264eaa0eSValentin Longchamp /* 48*264eaa0eSValentin Longchamp * DDR Setup 49*264eaa0eSValentin Longchamp */ 50*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 51*264eaa0eSValentin Longchamp #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 52*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 53*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 54*264eaa0eSValentin Longchamp DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 55*264eaa0eSValentin Longchamp 56*264eaa0eSValentin Longchamp #define CFG_83XX_DDR_USES_CS0 57*264eaa0eSValentin Longchamp 58*264eaa0eSValentin Longchamp /* 59*264eaa0eSValentin Longchamp * Manually set up DDR parameters 60*264eaa0eSValentin Longchamp */ 61*264eaa0eSValentin Longchamp #define CONFIG_DDR_II 62*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ 63*264eaa0eSValentin Longchamp 64*264eaa0eSValentin Longchamp /* 65*264eaa0eSValentin Longchamp * The reserved memory 66*264eaa0eSValentin Longchamp */ 67*264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 68*264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BASE 0xF0000000 69*264eaa0eSValentin Longchamp 70*264eaa0eSValentin Longchamp #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 71*264eaa0eSValentin Longchamp #define CONFIG_SYS_RAMBOOT 72*264eaa0eSValentin Longchamp #endif 73*264eaa0eSValentin Longchamp 74*264eaa0eSValentin Longchamp /* Reserve 768 kB for Mon */ 75*264eaa0eSValentin Longchamp #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 76*264eaa0eSValentin Longchamp 77*264eaa0eSValentin Longchamp /* 78*264eaa0eSValentin Longchamp * Initial RAM Base Address Setup 79*264eaa0eSValentin Longchamp */ 80*264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_LOCK 81*264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 82*264eaa0eSValentin Longchamp #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ 83*264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 84*264eaa0eSValentin Longchamp #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 85*264eaa0eSValentin Longchamp GENERATED_GBL_DATA_SIZE) 86*264eaa0eSValentin Longchamp 87*264eaa0eSValentin Longchamp /* 88*264eaa0eSValentin Longchamp * Init Local Bus Memory Controller: 89*264eaa0eSValentin Longchamp * 90*264eaa0eSValentin Longchamp * Bank Bus Machine PortSz Size Device 91*264eaa0eSValentin Longchamp * ---- --- ------- ------ ----- ------ 92*264eaa0eSValentin Longchamp * 0 Local GPCM 16 bit 256MB FLASH 93*264eaa0eSValentin Longchamp * 1 Local GPCM 8 bit 128MB GPIO/PIGGY 94*264eaa0eSValentin Longchamp * 95*264eaa0eSValentin Longchamp */ 96*264eaa0eSValentin Longchamp /* 97*264eaa0eSValentin Longchamp * FLASH on the Local Bus 98*264eaa0eSValentin Longchamp */ 99*264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 100*264eaa0eSValentin Longchamp #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 101*264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ 102*264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_PROTECTION 103*264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 104*264eaa0eSValentin Longchamp 105*264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 106*264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ 107*264eaa0eSValentin Longchamp 108*264eaa0eSValentin Longchamp #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 109*264eaa0eSValentin Longchamp (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 110*264eaa0eSValentin Longchamp BR_V) 111*264eaa0eSValentin Longchamp 112*264eaa0eSValentin Longchamp #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ 113*264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 114*264eaa0eSValentin Longchamp OR_GPCM_SCY_5 | \ 115*264eaa0eSValentin Longchamp OR_GPCM_TRLX | OR_GPCM_EAD) 116*264eaa0eSValentin Longchamp 117*264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 118*264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 119*264eaa0eSValentin Longchamp #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 120*264eaa0eSValentin Longchamp 121*264eaa0eSValentin Longchamp /* 122*264eaa0eSValentin Longchamp * PRIO1/PIGGY on the local bus CS1 123*264eaa0eSValentin Longchamp */ 124*264eaa0eSValentin Longchamp /* Window base at flash base */ 125*264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE 126*264eaa0eSValentin Longchamp #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ 127*264eaa0eSValentin Longchamp 128*264eaa0eSValentin Longchamp #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ 129*264eaa0eSValentin Longchamp (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ 130*264eaa0eSValentin Longchamp BR_V) 131*264eaa0eSValentin Longchamp #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ 132*264eaa0eSValentin Longchamp OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 133*264eaa0eSValentin Longchamp OR_GPCM_SCY_2 | \ 134*264eaa0eSValentin Longchamp OR_GPCM_TRLX | OR_GPCM_EAD) 135*264eaa0eSValentin Longchamp 136*264eaa0eSValentin Longchamp /* 137*264eaa0eSValentin Longchamp * Serial Port 138*264eaa0eSValentin Longchamp */ 139*264eaa0eSValentin Longchamp #define CONFIG_CONS_INDEX 1 140*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550 141*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_SERIAL 142*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_REG_SIZE 1 143*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 144*264eaa0eSValentin Longchamp 145*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 146*264eaa0eSValentin Longchamp #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 147*264eaa0eSValentin Longchamp 148*264eaa0eSValentin Longchamp /* Pass open firmware flat tree */ 149*264eaa0eSValentin Longchamp #define CONFIG_OF_LIBFDT 150*264eaa0eSValentin Longchamp #define CONFIG_OF_BOARD_SETUP 151*264eaa0eSValentin Longchamp #define CONFIG_OF_STDOUT_VIA_ALIAS 152*264eaa0eSValentin Longchamp 153*264eaa0eSValentin Longchamp #ifndef CONFIG_NET_MULTI 154*264eaa0eSValentin Longchamp #define CONFIG_NET_MULTI 155*264eaa0eSValentin Longchamp #endif 156*264eaa0eSValentin Longchamp /* 157*264eaa0eSValentin Longchamp * QE UEC ethernet configuration 158*264eaa0eSValentin Longchamp */ 159*264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH 160*264eaa0eSValentin Longchamp #define CONFIG_ETHPRIME "UEC0" 161*264eaa0eSValentin Longchamp 162*264eaa0eSValentin Longchamp #define CONFIG_UEC_ETH1 /* GETH1 */ 163*264eaa0eSValentin Longchamp #define UEC_VERBOSE_DEBUG 1 164*264eaa0eSValentin Longchamp 165*264eaa0eSValentin Longchamp #ifdef CONFIG_UEC_ETH1 166*264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ 167*264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 168*264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 169*264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 170*264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_PHY_ADDR 0 171*264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 172*264eaa0eSValentin Longchamp #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 173*264eaa0eSValentin Longchamp #endif 174*264eaa0eSValentin Longchamp 175*264eaa0eSValentin Longchamp /* 176*264eaa0eSValentin Longchamp * Environment 177*264eaa0eSValentin Longchamp */ 178*264eaa0eSValentin Longchamp 179*264eaa0eSValentin Longchamp #ifndef CONFIG_SYS_RAMBOOT 180*264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_IN_FLASH 181*264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 182*264eaa0eSValentin Longchamp CONFIG_SYS_MONITOR_LEN) 183*264eaa0eSValentin Longchamp #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 184*264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) 185*264eaa0eSValentin Longchamp 186*264eaa0eSValentin Longchamp /* Address and size of Redundant Environment Sector */ 187*264eaa0eSValentin Longchamp #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 188*264eaa0eSValentin Longchamp CONFIG_ENV_SECT_SIZE) 189*264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 190*264eaa0eSValentin Longchamp 191*264eaa0eSValentin Longchamp #else /* CFG_SYS_RAMBOOT */ 192*264eaa0eSValentin Longchamp #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 193*264eaa0eSValentin Longchamp #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 194*264eaa0eSValentin Longchamp #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 195*264eaa0eSValentin Longchamp #define CONFIG_ENV_SIZE 0x2000 196*264eaa0eSValentin Longchamp #endif /* CFG_SYS_RAMBOOT */ 197*264eaa0eSValentin Longchamp 198*264eaa0eSValentin Longchamp /* I2C */ 199*264eaa0eSValentin Longchamp #define CONFIG_HARD_I2C /* I2C with hardware support */ 200*264eaa0eSValentin Longchamp #define CONFIG_FSL_I2C 201*264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */ 202*264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_SLAVE 0x7F 203*264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_OFFSET 0x3000 204*264eaa0eSValentin Longchamp 205*264eaa0eSValentin Longchamp /* I2C SYSMON (LM75, AD7414 is almost compatible) */ 206*264eaa0eSValentin Longchamp #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ 207*264eaa0eSValentin Longchamp #define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ 208*264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_MAX_TEMP 70 209*264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_LOW_TEMP -30 210*264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_HYSTERESIS 3 211*264eaa0eSValentin Longchamp #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) 212*264eaa0eSValentin Longchamp 213*264eaa0eSValentin Longchamp #if defined(CONFIG_CMD_NAND) 214*264eaa0eSValentin Longchamp #define CONFIG_NAND_KMETER1 215*264eaa0eSValentin Longchamp #define CONFIG_SYS_MAX_NAND_DEVICE 1 216*264eaa0eSValentin Longchamp #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE 217*264eaa0eSValentin Longchamp #endif 218*264eaa0eSValentin Longchamp 219*264eaa0eSValentin Longchamp #if defined(CONFIG_PCI) 220*264eaa0eSValentin Longchamp #define CONFIG_CMD_PCI 221*264eaa0eSValentin Longchamp #endif 222*264eaa0eSValentin Longchamp 223*264eaa0eSValentin Longchamp /* 224*264eaa0eSValentin Longchamp * For booting Linux, the board info and command line data 225*264eaa0eSValentin Longchamp * have to be in the first 8 MB of memory, since this is 226*264eaa0eSValentin Longchamp * the maximum mapped by the Linux kernel during initialization. 227*264eaa0eSValentin Longchamp */ 228*264eaa0eSValentin Longchamp #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 229*264eaa0eSValentin Longchamp 230*264eaa0eSValentin Longchamp /* 231*264eaa0eSValentin Longchamp * Core HID Setup 232*264eaa0eSValentin Longchamp */ 233*264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_INIT 0x000000000 234*264eaa0eSValentin Longchamp #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 235*264eaa0eSValentin Longchamp HID0_ENABLE_INSTRUCTION_CACHE) 236*264eaa0eSValentin Longchamp #define CONFIG_SYS_HID2 HID2_HBE 237*264eaa0eSValentin Longchamp 238*264eaa0eSValentin Longchamp /* 239*264eaa0eSValentin Longchamp * MMU Setup 240*264eaa0eSValentin Longchamp */ 241*264eaa0eSValentin Longchamp 242*264eaa0eSValentin Longchamp #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 243*264eaa0eSValentin Longchamp 244*264eaa0eSValentin Longchamp /* DDR: cache cacheable */ 245*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ 246*264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 247*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 248*264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 249*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 250*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 251*264eaa0eSValentin Longchamp 252*264eaa0eSValentin Longchamp /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 253*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 254*264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 255*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ 256*264eaa0eSValentin Longchamp | BATU_VP) 257*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 258*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 259*264eaa0eSValentin Longchamp 260*264eaa0eSValentin Longchamp /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ 261*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ 262*264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 263*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ 264*264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 265*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ 266*264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 267*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 268*264eaa0eSValentin Longchamp 269*264eaa0eSValentin Longchamp /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 270*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 271*264eaa0eSValentin Longchamp BATL_MEMCOHERENCE) 272*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ 273*264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 274*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 275*264eaa0eSValentin Longchamp BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 276*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 277*264eaa0eSValentin Longchamp 278*264eaa0eSValentin Longchamp /* Stack in dcache: cacheable, no memory coherence */ 279*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 280*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 281*264eaa0eSValentin Longchamp BATU_VS | BATU_VP) 282*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 283*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 284*264eaa0eSValentin Longchamp 285*264eaa0eSValentin Longchamp /* 286*264eaa0eSValentin Longchamp * Internal Definitions 287*264eaa0eSValentin Longchamp * 288*264eaa0eSValentin Longchamp * Boot Flags 289*264eaa0eSValentin Longchamp */ 290*264eaa0eSValentin Longchamp #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 291*264eaa0eSValentin Longchamp #define BOOTFLAG_WARM 0x02 /* Software reboot */ 292*264eaa0eSValentin Longchamp 293*264eaa0eSValentin Longchamp #define BOOTFLASH_START 0xF0000000 294*264eaa0eSValentin Longchamp 295*264eaa0eSValentin Longchamp #define CONFIG_KM_CONSOLE_TTY "ttyS0" 296*264eaa0eSValentin Longchamp 297*264eaa0eSValentin Longchamp /* 298*264eaa0eSValentin Longchamp * Environment Configuration 299*264eaa0eSValentin Longchamp */ 300*264eaa0eSValentin Longchamp #define CONFIG_ENV_OVERWRITE 301*264eaa0eSValentin Longchamp #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ 302*264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ENV "km-common=empty\0" 303*264eaa0eSValentin Longchamp #endif 304*264eaa0eSValentin Longchamp 305*264eaa0eSValentin Longchamp #ifndef CONFIG_KM_DEF_ROOTPATH 306*264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ROOTPATH \ 307*264eaa0eSValentin Longchamp "rootpath=/opt/eldk/ppc_82xx\0" 308*264eaa0eSValentin Longchamp #endif 309*264eaa0eSValentin Longchamp 310*264eaa0eSValentin Longchamp #define CONFIG_EXTRA_ENV_SETTINGS \ 311*264eaa0eSValentin Longchamp CONFIG_KM_DEF_ENV \ 312*264eaa0eSValentin Longchamp CONFIG_KM_DEF_ROOTPATH \ 313*264eaa0eSValentin Longchamp "dtt_bus=pca9547:70:a\0" \ 314*264eaa0eSValentin Longchamp "EEprom_ivm=pca9547:70:9\0" \ 315*264eaa0eSValentin Longchamp "newenv=" \ 316*264eaa0eSValentin Longchamp "prot off 0xF00C0000 +0x40000 && " \ 317*264eaa0eSValentin Longchamp "era 0xF00C0000 +0x40000\0" \ 318*264eaa0eSValentin Longchamp "unlock=yes\0" \ 319*264eaa0eSValentin Longchamp "" 320*264eaa0eSValentin Longchamp 321*264eaa0eSValentin Longchamp #if defined(CONFIG_UEC_ETH) 322*264eaa0eSValentin Longchamp #define CONFIG_HAS_ETH0 323*264eaa0eSValentin Longchamp #endif 324*264eaa0eSValentin Longchamp 325*264eaa0eSValentin Longchamp #endif /* __CONFIG_KM83XX_H */ 326