1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2008 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * (C) Copyright 2010 15 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com 16 * 17 * (C) Copyright 2010-2011 18 * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com 19 * 20 * SPDX-License-Identifier: GPL-2.0+ 21 */ 22 23 #ifndef __CONFIG_KM8321_COMMON_H 24 #define __CONFIG_KM8321_COMMON_H 25 26 #define CONFIG_DISPLAY_BOARDINFO 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_QE /* Has QE */ 32 #define CONFIG_MPC832x /* MPC832x CPU specific */ 33 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ 34 35 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" 36 37 /* include common defines/options for all 83xx Keymile boards */ 38 #include "km83xx-common.h" 39 40 /* 41 * System IO Config 42 */ 43 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS 44 45 /* 46 * Hardware Reset Configuration Word 47 */ 48 #define CONFIG_SYS_HRCW_LOW (\ 49 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 50 HRCWL_DDR_TO_SCB_CLK_2X1 | \ 51 HRCWL_CSB_TO_CLKIN_2X1 | \ 52 HRCWL_CORE_TO_CSB_2_5X1 | \ 53 HRCWL_CE_PLL_VCO_DIV_2 | \ 54 HRCWL_CE_TO_PLL_1X3) 55 56 #define CONFIG_SYS_HRCW_HIGH (\ 57 HRCWH_PCI_AGENT | \ 58 HRCWH_PCI_ARBITER_DISABLE | \ 59 HRCWH_CORE_ENABLE | \ 60 HRCWH_FROM_0X00000100 | \ 61 HRCWH_BOOTSEQ_DISABLE | \ 62 HRCWH_SW_WATCHDOG_DISABLE | \ 63 HRCWH_ROM_LOC_LOCAL_16BIT | \ 64 HRCWH_BIG_ENDIAN | \ 65 HRCWH_LALE_NORMAL) 66 67 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 68 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 69 SDRAM_CFG_32_BE | \ 70 SDRAM_CFG_SREN | \ 71 SDRAM_CFG_HSE) 72 73 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 74 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 75 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 76 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 77 78 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 79 CSCONFIG_ODT_WR_CFG | \ 80 CSCONFIG_ROW_BIT_13 | \ 81 CSCONFIG_COL_BIT_10) 82 83 #define CONFIG_SYS_DDR_MODE 0x47860242 84 #define CONFIG_SYS_DDR_MODE2 0x8080c000 85 86 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 87 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 88 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 89 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 90 (0 << TIMING_CFG0_WWT_SHIFT) | \ 91 (0 << TIMING_CFG0_RRT_SHIFT) | \ 92 (0 << TIMING_CFG0_WRT_SHIFT) | \ 93 (0 << TIMING_CFG0_RWT_SHIFT)) 94 95 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 96 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 97 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 98 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 99 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 100 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 101 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 102 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 103 104 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 105 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 106 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 107 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 108 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 109 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 110 (5 << TIMING_CFG2_CPO_SHIFT)) 111 112 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 113 114 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 115 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 116 117 /* EEprom support */ 118 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 119 120 /* 121 * Local Bus Configuration & Clock Setup 122 */ 123 #define CONFIG_SYS_LCRR_DBYP 0x80000000 124 #define CONFIG_SYS_LCRR_EADC 0x00010000 125 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002 126 127 #define CONFIG_SYS_LBC_LBCR 0x00000000 128 129 /* 130 * MMU Setup 131 */ 132 #define CONFIG_SYS_IBAT7L (0) 133 #define CONFIG_SYS_IBAT7U (0) 134 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 135 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 136 137 #endif /* __CONFIG_KM8321_COMMON_H */ 138