1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2008 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * (C) Copyright 2010 15 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com 16 * 17 * (C) Copyright 2010-2011 18 * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com 19 * 20 * SPDX-License-Identifier: GPL-2.0+ 21 */ 22 23 #ifndef __CONFIG_KM8321_COMMON_H 24 #define __CONFIG_KM8321_COMMON_H 25 26 /* 27 * High Level Configuration Options 28 */ 29 #define CONFIG_QE /* Has QE */ 30 #define CONFIG_MPC832x /* MPC832x CPU specific */ 31 #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ 32 33 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" 34 35 /* include common defines/options for all 83xx Keymile boards */ 36 #include "km83xx-common.h" 37 38 /* 39 * System IO Config 40 */ 41 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS 42 43 /* 44 * Hardware Reset Configuration Word 45 */ 46 #define CONFIG_SYS_HRCW_LOW (\ 47 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 48 HRCWL_DDR_TO_SCB_CLK_2X1 | \ 49 HRCWL_CSB_TO_CLKIN_2X1 | \ 50 HRCWL_CORE_TO_CSB_2_5X1 | \ 51 HRCWL_CE_PLL_VCO_DIV_2 | \ 52 HRCWL_CE_TO_PLL_1X3) 53 54 #define CONFIG_SYS_HRCW_HIGH (\ 55 HRCWH_PCI_AGENT | \ 56 HRCWH_PCI_ARBITER_DISABLE | \ 57 HRCWH_CORE_ENABLE | \ 58 HRCWH_FROM_0X00000100 | \ 59 HRCWH_BOOTSEQ_DISABLE | \ 60 HRCWH_SW_WATCHDOG_DISABLE | \ 61 HRCWH_ROM_LOC_LOCAL_16BIT | \ 62 HRCWH_BIG_ENDIAN | \ 63 HRCWH_LALE_NORMAL) 64 65 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 66 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 67 SDRAM_CFG_32_BE | \ 68 SDRAM_CFG_SREN | \ 69 SDRAM_CFG_HSE) 70 71 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 72 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 73 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 74 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 75 76 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 77 CSCONFIG_ODT_WR_CFG | \ 78 CSCONFIG_ROW_BIT_13 | \ 79 CSCONFIG_COL_BIT_10) 80 81 #define CONFIG_SYS_DDR_MODE 0x47860242 82 #define CONFIG_SYS_DDR_MODE2 0x8080c000 83 84 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 85 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 86 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 87 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 88 (0 << TIMING_CFG0_WWT_SHIFT) | \ 89 (0 << TIMING_CFG0_RRT_SHIFT) | \ 90 (0 << TIMING_CFG0_WRT_SHIFT) | \ 91 (0 << TIMING_CFG0_RWT_SHIFT)) 92 93 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 94 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 95 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 96 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 97 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 98 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 99 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 100 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 101 102 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 103 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 104 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 105 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 106 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 107 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 108 (5 << TIMING_CFG2_CPO_SHIFT)) 109 110 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 111 112 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 113 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 114 115 /* EEprom support */ 116 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 117 118 /* 119 * Local Bus Configuration & Clock Setup 120 */ 121 #define CONFIG_SYS_LCRR_DBYP 0x80000000 122 #define CONFIG_SYS_LCRR_EADC 0x00010000 123 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002 124 125 #define CONFIG_SYS_LBC_LBCR 0x00000000 126 127 /* 128 * MMU Setup 129 */ 130 #define CONFIG_SYS_IBAT7L (0) 131 #define CONFIG_SYS_IBAT7U (0) 132 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 133 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 134 135 #endif /* __CONFIG_KM8321_COMMON_H */ 136