1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *                    Dave Liu <daveliu@freescale.com>
4  *
5  * Copyright (C) 2007 Logic Product Development, Inc.
6  *                    Peter Barada <peterb@logicpd.com>
7  *
8  * Copyright (C) 2007 MontaVista Software, Inc.
9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
10  *
11  * (C) Copyright 2008
12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13  *
14  * (C) Copyright 2010
15  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
16  *
17  * (C) Copyright 2010-2011
18  * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
19  *
20  * SPDX-License-Identifier:	GPL-2.0+
21  */
22 
23 #ifndef __CONFIG_KM8321_COMMON_H
24 #define __CONFIG_KM8321_COMMON_H
25 
26 /*
27  * High Level Configuration Options
28  */
29 #define CONFIG_QE	/* Has QE */
30 #define CONFIG_MPC832x	/* MPC832x CPU specific */
31 #define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
32 
33 #define CONFIG_KM_DEF_ARCH	"arch=ppc_8xx\0"
34 
35 /* include common defines/options for all 83xx Keymile boards */
36 #include "km83xx-common.h"
37 
38 /*
39  * System IO Config
40  */
41 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
42 
43 /*
44  * Hardware Reset Configuration Word
45  */
46 #define CONFIG_SYS_HRCW_LOW (\
47 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
48 	HRCWL_DDR_TO_SCB_CLK_2X1 | \
49 	HRCWL_CSB_TO_CLKIN_2X1 | \
50 	HRCWL_CORE_TO_CSB_2_5X1 | \
51 	HRCWL_CE_PLL_VCO_DIV_2 | \
52 	HRCWL_CE_TO_PLL_1X3)
53 
54 #define CONFIG_SYS_HRCW_HIGH (\
55 	HRCWH_PCI_AGENT | \
56 	HRCWH_PCI_ARBITER_DISABLE | \
57 	HRCWH_CORE_ENABLE | \
58 	HRCWH_FROM_0X00000100 | \
59 	HRCWH_BOOTSEQ_DISABLE | \
60 	HRCWH_SW_WATCHDOG_DISABLE | \
61 	HRCWH_ROM_LOC_LOCAL_16BIT | \
62 	HRCWH_BIG_ENDIAN | \
63 	HRCWH_LALE_NORMAL)
64 
65 #define CONFIG_SYS_DDRCDR (\
66 	DDRCDR_EN | \
67 	DDRCDR_PZ_MAXZ | \
68 	DDRCDR_NZ_MAXZ | \
69 	DDRCDR_M_ODR)
70 
71 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
72 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
73 					 SDRAM_CFG_32_BE | \
74 					 SDRAM_CFG_SREN | \
75 					 SDRAM_CFG_HSE)
76 
77 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
78 #define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
79 #define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
80 				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
81 
82 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
83 					 CSCONFIG_ODT_WR_CFG | \
84 					 CSCONFIG_ROW_BIT_13 | \
85 					 CSCONFIG_COL_BIT_10)
86 
87 #define CONFIG_SYS_DDR_MODE	0x47860242
88 #define CONFIG_SYS_DDR_MODE2	0x8080c000
89 
90 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
91 				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
92 				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
93 				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
94 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
95 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
96 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
97 				 (0 << TIMING_CFG0_RWT_SHIFT))
98 
99 #define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
100 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
101 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
102 				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
103 				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
104 				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
105 				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
106 				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
107 
108 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
109 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
110 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
111 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
112 				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
113 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
114 				 (5 << TIMING_CFG2_CPO_SHIFT))
115 
116 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
117 
118 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
119 #define CONFIG_SYS_KMBEC_FPGA_SIZE	128
120 
121 /* EEprom support */
122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
123 
124 /*
125  * Local Bus Configuration & Clock Setup
126  */
127 #define CONFIG_SYS_LCRR_DBYP	0x80000000
128 #define CONFIG_SYS_LCRR_EADC	0x00010000
129 #define CONFIG_SYS_LCRR_CLKDIV	0x00000002
130 
131 #define CONFIG_SYS_LBC_LBCR	0x00000000
132 
133 /*
134  * MMU Setup
135  */
136 #define CONFIG_SYS_IBAT7L	(0)
137 #define CONFIG_SYS_IBAT7U	(0)
138 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
139 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
140 
141 #endif /* __CONFIG_KM8321_COMMON_H */
142