1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *                    Dave Liu <daveliu@freescale.com>
4  *
5  * Copyright (C) 2007 Logic Product Development, Inc.
6  *                    Peter Barada <peterb@logicpd.com>
7  *
8  * Copyright (C) 2007 MontaVista Software, Inc.
9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
10  *
11  * (C) Copyright 2008
12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13  *
14  * (C) Copyright 2010
15  * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
16  *
17  * (C) Copyright 2010-2011
18  * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
19  *
20  * SPDX-License-Identifier:	GPL-2.0+
21  */
22 
23 #ifndef __CONFIG_KM8321_COMMON_H
24 #define __CONFIG_KM8321_COMMON_H
25 
26 #define CONFIG_SYS_GENERIC_BOARD
27 #define CONFIG_DISPLAY_BOARDINFO
28 
29 /*
30  * High Level Configuration Options
31  */
32 #define CONFIG_QE	/* Has QE */
33 #define CONFIG_MPC832x	/* MPC832x CPU specific */
34 #define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
35 
36 #define CONFIG_KM_DEF_ARCH	"arch=ppc_8xx\0"
37 
38 /* include common defines/options for all 83xx Keymile boards */
39 #include "km83xx-common.h"
40 
41 /*
42  * System IO Config
43  */
44 #define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
45 
46 /*
47  * Hardware Reset Configuration Word
48  */
49 #define CONFIG_SYS_HRCW_LOW (\
50 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
51 	HRCWL_DDR_TO_SCB_CLK_2X1 | \
52 	HRCWL_CSB_TO_CLKIN_2X1 | \
53 	HRCWL_CORE_TO_CSB_2_5X1 | \
54 	HRCWL_CE_PLL_VCO_DIV_2 | \
55 	HRCWL_CE_TO_PLL_1X3)
56 
57 #define CONFIG_SYS_HRCW_HIGH (\
58 	HRCWH_PCI_AGENT | \
59 	HRCWH_PCI_ARBITER_DISABLE | \
60 	HRCWH_CORE_ENABLE | \
61 	HRCWH_FROM_0X00000100 | \
62 	HRCWH_BOOTSEQ_DISABLE | \
63 	HRCWH_SW_WATCHDOG_DISABLE | \
64 	HRCWH_ROM_LOC_LOCAL_16BIT | \
65 	HRCWH_BIG_ENDIAN | \
66 	HRCWH_LALE_NORMAL)
67 
68 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
69 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
70 					 SDRAM_CFG_32_BE | \
71 					 SDRAM_CFG_SREN | \
72 					 SDRAM_CFG_HSE)
73 
74 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
75 #define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
76 #define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
77 				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
78 
79 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
80 					 CSCONFIG_ODT_WR_CFG | \
81 					 CSCONFIG_ROW_BIT_13 | \
82 					 CSCONFIG_COL_BIT_10)
83 
84 #define CONFIG_SYS_DDR_MODE	0x47860242
85 #define CONFIG_SYS_DDR_MODE2	0x8080c000
86 
87 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
88 				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
89 				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
90 				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
91 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
92 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
93 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
94 				 (0 << TIMING_CFG0_RWT_SHIFT))
95 
96 #define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
97 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
98 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
99 				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
100 				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
101 				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
102 				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
103 				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
104 
105 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
106 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
107 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
108 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
109 				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
110 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
111 				 (5 << TIMING_CFG2_CPO_SHIFT))
112 
113 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
114 
115 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
116 #define CONFIG_SYS_KMBEC_FPGA_SIZE	128
117 
118 /* EEprom support */
119 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
120 
121 /*
122  * Local Bus Configuration & Clock Setup
123  */
124 #define CONFIG_SYS_LCRR_DBYP	0x80000000
125 #define CONFIG_SYS_LCRR_EADC	0x00010000
126 #define CONFIG_SYS_LCRR_CLKDIV	0x00000002
127 
128 #define CONFIG_SYS_LBC_LBCR	0x00000000
129 
130 /*
131  * MMU Setup
132  */
133 #define CONFIG_SYS_IBAT7L	(0)
134 #define CONFIG_SYS_IBAT7U	(0)
135 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
136 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
137 
138 #endif /* __CONFIG_KM8321_COMMON_H */
139