1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2264eaa0eSValentin Longchamp /* 3264eaa0eSValentin Longchamp * Copyright (C) 2006 Freescale Semiconductor, Inc. 4264eaa0eSValentin Longchamp * Dave Liu <daveliu@freescale.com> 5264eaa0eSValentin Longchamp * 6264eaa0eSValentin Longchamp * Copyright (C) 2007 Logic Product Development, Inc. 7264eaa0eSValentin Longchamp * Peter Barada <peterb@logicpd.com> 8264eaa0eSValentin Longchamp * 9264eaa0eSValentin Longchamp * Copyright (C) 2007 MontaVista Software, Inc. 10264eaa0eSValentin Longchamp * Anton Vorontsov <avorontsov@ru.mvista.com> 11264eaa0eSValentin Longchamp * 12264eaa0eSValentin Longchamp * (C) Copyright 2008 13264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 14264eaa0eSValentin Longchamp * 15264eaa0eSValentin Longchamp * (C) Copyright 2010 16264eaa0eSValentin Longchamp * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com 17264eaa0eSValentin Longchamp * 18264eaa0eSValentin Longchamp * (C) Copyright 2010-2011 19264eaa0eSValentin Longchamp * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com 20264eaa0eSValentin Longchamp */ 21264eaa0eSValentin Longchamp 22264eaa0eSValentin Longchamp #ifndef __CONFIG_KM8321_COMMON_H 23264eaa0eSValentin Longchamp #define __CONFIG_KM8321_COMMON_H 24264eaa0eSValentin Longchamp 25264eaa0eSValentin Longchamp /* 26264eaa0eSValentin Longchamp * High Level Configuration Options 27264eaa0eSValentin Longchamp */ 28264eaa0eSValentin Longchamp #define CONFIG_QE /* Has QE */ 29264eaa0eSValentin Longchamp #define CONFIG_MPC832x /* MPC832x CPU specific */ 30264eaa0eSValentin Longchamp #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ 31264eaa0eSValentin Longchamp 32b648bfc2SHolger Brunck #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" 33264eaa0eSValentin Longchamp 34264eaa0eSValentin Longchamp /* include common defines/options for all 83xx Keymile boards */ 35264eaa0eSValentin Longchamp #include "km83xx-common.h" 36264eaa0eSValentin Longchamp 37264eaa0eSValentin Longchamp /* 38264eaa0eSValentin Longchamp * System IO Config 39264eaa0eSValentin Longchamp */ 40264eaa0eSValentin Longchamp #define CONFIG_SYS_SICRL SICRL_IRQ_CKS 41264eaa0eSValentin Longchamp 42264eaa0eSValentin Longchamp /* 43264eaa0eSValentin Longchamp * Hardware Reset Configuration Word 44264eaa0eSValentin Longchamp */ 45264eaa0eSValentin Longchamp #define CONFIG_SYS_HRCW_LOW (\ 46264eaa0eSValentin Longchamp HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 47264eaa0eSValentin Longchamp HRCWL_DDR_TO_SCB_CLK_2X1 | \ 48264eaa0eSValentin Longchamp HRCWL_CSB_TO_CLKIN_2X1 | \ 49264eaa0eSValentin Longchamp HRCWL_CORE_TO_CSB_2_5X1 | \ 50264eaa0eSValentin Longchamp HRCWL_CE_PLL_VCO_DIV_2 | \ 51264eaa0eSValentin Longchamp HRCWL_CE_TO_PLL_1X3) 52264eaa0eSValentin Longchamp 53264eaa0eSValentin Longchamp #define CONFIG_SYS_HRCW_HIGH (\ 54264eaa0eSValentin Longchamp HRCWH_PCI_AGENT | \ 55264eaa0eSValentin Longchamp HRCWH_PCI_ARBITER_DISABLE | \ 56264eaa0eSValentin Longchamp HRCWH_CORE_ENABLE | \ 57264eaa0eSValentin Longchamp HRCWH_FROM_0X00000100 | \ 58264eaa0eSValentin Longchamp HRCWH_BOOTSEQ_DISABLE | \ 59264eaa0eSValentin Longchamp HRCWH_SW_WATCHDOG_DISABLE | \ 60264eaa0eSValentin Longchamp HRCWH_ROM_LOC_LOCAL_16BIT | \ 61264eaa0eSValentin Longchamp HRCWH_BIG_ENDIAN | \ 62264eaa0eSValentin Longchamp HRCWH_LALE_NORMAL) 63264eaa0eSValentin Longchamp 64d4bd2ca2SValentin Longchamp #define CONFIG_SYS_DDRCDR (\ 65d4bd2ca2SValentin Longchamp DDRCDR_EN | \ 66d4bd2ca2SValentin Longchamp DDRCDR_PZ_MAXZ | \ 67d4bd2ca2SValentin Longchamp DDRCDR_NZ_MAXZ | \ 68d4bd2ca2SValentin Longchamp DDRCDR_M_ODR) 69d4bd2ca2SValentin Longchamp 70264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 71264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 72264eaa0eSValentin Longchamp SDRAM_CFG_32_BE | \ 73513e396bSMarco Schmid SDRAM_CFG_SREN | \ 74513e396bSMarco Schmid SDRAM_CFG_HSE) 75264eaa0eSValentin Longchamp 76264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 77264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 78264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 79264eaa0eSValentin Longchamp (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 80264eaa0eSValentin Longchamp 81264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 82264eaa0eSValentin Longchamp CSCONFIG_ODT_WR_CFG | \ 83264eaa0eSValentin Longchamp CSCONFIG_ROW_BIT_13 | \ 84264eaa0eSValentin Longchamp CSCONFIG_COL_BIT_10) 85264eaa0eSValentin Longchamp 86513e396bSMarco Schmid #define CONFIG_SYS_DDR_MODE 0x47860242 87264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_MODE2 0x8080c000 88264eaa0eSValentin Longchamp 89264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 90264eaa0eSValentin Longchamp (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 91264eaa0eSValentin Longchamp (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 92264eaa0eSValentin Longchamp (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 93264eaa0eSValentin Longchamp (0 << TIMING_CFG0_WWT_SHIFT) | \ 94264eaa0eSValentin Longchamp (0 << TIMING_CFG0_RRT_SHIFT) | \ 95264eaa0eSValentin Longchamp (0 << TIMING_CFG0_WRT_SHIFT) | \ 96264eaa0eSValentin Longchamp (0 << TIMING_CFG0_RWT_SHIFT)) 97264eaa0eSValentin Longchamp 98513e396bSMarco Schmid #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 99264eaa0eSValentin Longchamp (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 100264eaa0eSValentin Longchamp (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 101513e396bSMarco Schmid (3 << TIMING_CFG1_WRREC_SHIFT) | \ 102513e396bSMarco Schmid (7 << TIMING_CFG1_REFREC_SHIFT) | \ 103513e396bSMarco Schmid (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 104513e396bSMarco Schmid (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 105513e396bSMarco Schmid (3 << TIMING_CFG1_PRETOACT_SHIFT)) 106264eaa0eSValentin Longchamp 107264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 108264eaa0eSValentin Longchamp (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 109264eaa0eSValentin Longchamp (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 110264eaa0eSValentin Longchamp (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 111513e396bSMarco Schmid (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 112264eaa0eSValentin Longchamp (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 113264eaa0eSValentin Longchamp (5 << TIMING_CFG2_CPO_SHIFT)) 114264eaa0eSValentin Longchamp 115264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_TIMING_3 0x00000000 116264eaa0eSValentin Longchamp 117264eaa0eSValentin Longchamp #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 118264eaa0eSValentin Longchamp #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 119264eaa0eSValentin Longchamp 120264eaa0eSValentin Longchamp /* EEprom support */ 121264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 122264eaa0eSValentin Longchamp 123264eaa0eSValentin Longchamp /* 124264eaa0eSValentin Longchamp * Local Bus Configuration & Clock Setup 125264eaa0eSValentin Longchamp */ 126513e396bSMarco Schmid #define CONFIG_SYS_LCRR_DBYP 0x80000000 127513e396bSMarco Schmid #define CONFIG_SYS_LCRR_EADC 0x00010000 128513e396bSMarco Schmid #define CONFIG_SYS_LCRR_CLKDIV 0x00000002 129513e396bSMarco Schmid 130264eaa0eSValentin Longchamp #define CONFIG_SYS_LBC_LBCR 0x00000000 131264eaa0eSValentin Longchamp 132264eaa0eSValentin Longchamp /* 133264eaa0eSValentin Longchamp * MMU Setup 134264eaa0eSValentin Longchamp */ 135264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT7L (0) 136264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT7U (0) 137264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 138264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 139264eaa0eSValentin Longchamp 140264eaa0eSValentin Longchamp #endif /* __CONFIG_KM8321_COMMON_H */ 141