1*264eaa0eSValentin Longchamp /* 2*264eaa0eSValentin Longchamp * Copyright (C) 2006 Freescale Semiconductor, Inc. 3*264eaa0eSValentin Longchamp * Dave Liu <daveliu@freescale.com> 4*264eaa0eSValentin Longchamp * 5*264eaa0eSValentin Longchamp * Copyright (C) 2007 Logic Product Development, Inc. 6*264eaa0eSValentin Longchamp * Peter Barada <peterb@logicpd.com> 7*264eaa0eSValentin Longchamp * 8*264eaa0eSValentin Longchamp * Copyright (C) 2007 MontaVista Software, Inc. 9*264eaa0eSValentin Longchamp * Anton Vorontsov <avorontsov@ru.mvista.com> 10*264eaa0eSValentin Longchamp * 11*264eaa0eSValentin Longchamp * (C) Copyright 2008 12*264eaa0eSValentin Longchamp * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13*264eaa0eSValentin Longchamp * 14*264eaa0eSValentin Longchamp * (C) Copyright 2010 15*264eaa0eSValentin Longchamp * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com 16*264eaa0eSValentin Longchamp * 17*264eaa0eSValentin Longchamp * (C) Copyright 2010-2011 18*264eaa0eSValentin Longchamp * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com 19*264eaa0eSValentin Longchamp * 20*264eaa0eSValentin Longchamp * This program is free software; you can redistribute it and/or 21*264eaa0eSValentin Longchamp * modify it under the terms of the GNU General Public License as 22*264eaa0eSValentin Longchamp * published by the Free Software Foundation; either version 2 of 23*264eaa0eSValentin Longchamp * the License, or (at your option) any later version. 24*264eaa0eSValentin Longchamp */ 25*264eaa0eSValentin Longchamp 26*264eaa0eSValentin Longchamp #ifndef __CONFIG_KM8321_COMMON_H 27*264eaa0eSValentin Longchamp #define __CONFIG_KM8321_COMMON_H 28*264eaa0eSValentin Longchamp 29*264eaa0eSValentin Longchamp /* 30*264eaa0eSValentin Longchamp * High Level Configuration Options 31*264eaa0eSValentin Longchamp */ 32*264eaa0eSValentin Longchamp #define CONFIG_QE /* Has QE */ 33*264eaa0eSValentin Longchamp #define CONFIG_MPC832x /* MPC832x CPU specific */ 34*264eaa0eSValentin Longchamp #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ 35*264eaa0eSValentin Longchamp 36*264eaa0eSValentin Longchamp #define CONFIG_KM_DEF_ROOTPATH \ 37*264eaa0eSValentin Longchamp "rootpath=/opt/eldk/ppc_8xx\0" 38*264eaa0eSValentin Longchamp 39*264eaa0eSValentin Longchamp /* include common defines/options for all 83xx Keymile boards */ 40*264eaa0eSValentin Longchamp #include "km83xx-common.h" 41*264eaa0eSValentin Longchamp 42*264eaa0eSValentin Longchamp #define CONFIG_MISC_INIT_R 43*264eaa0eSValentin Longchamp 44*264eaa0eSValentin Longchamp /* 45*264eaa0eSValentin Longchamp * System IO Config 46*264eaa0eSValentin Longchamp */ 47*264eaa0eSValentin Longchamp #define CONFIG_SYS_SICRL SICRL_IRQ_CKS 48*264eaa0eSValentin Longchamp 49*264eaa0eSValentin Longchamp /* 50*264eaa0eSValentin Longchamp * Hardware Reset Configuration Word 51*264eaa0eSValentin Longchamp */ 52*264eaa0eSValentin Longchamp #define CONFIG_SYS_HRCW_LOW (\ 53*264eaa0eSValentin Longchamp HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 54*264eaa0eSValentin Longchamp HRCWL_DDR_TO_SCB_CLK_2X1 | \ 55*264eaa0eSValentin Longchamp HRCWL_CSB_TO_CLKIN_2X1 | \ 56*264eaa0eSValentin Longchamp HRCWL_CORE_TO_CSB_2_5X1 | \ 57*264eaa0eSValentin Longchamp HRCWL_CE_PLL_VCO_DIV_2 | \ 58*264eaa0eSValentin Longchamp HRCWL_CE_TO_PLL_1X3) 59*264eaa0eSValentin Longchamp 60*264eaa0eSValentin Longchamp #define CONFIG_SYS_HRCW_HIGH (\ 61*264eaa0eSValentin Longchamp HRCWH_PCI_AGENT | \ 62*264eaa0eSValentin Longchamp HRCWH_PCI_ARBITER_DISABLE | \ 63*264eaa0eSValentin Longchamp HRCWH_CORE_ENABLE | \ 64*264eaa0eSValentin Longchamp HRCWH_FROM_0X00000100 | \ 65*264eaa0eSValentin Longchamp HRCWH_BOOTSEQ_DISABLE | \ 66*264eaa0eSValentin Longchamp HRCWH_SW_WATCHDOG_DISABLE | \ 67*264eaa0eSValentin Longchamp HRCWH_ROM_LOC_LOCAL_16BIT | \ 68*264eaa0eSValentin Longchamp HRCWH_BIG_ENDIAN | \ 69*264eaa0eSValentin Longchamp HRCWH_LALE_NORMAL) 70*264eaa0eSValentin Longchamp 71*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 72*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 73*264eaa0eSValentin Longchamp SDRAM_CFG_32_BE | \ 74*264eaa0eSValentin Longchamp SDRAM_CFG_SREN) 75*264eaa0eSValentin Longchamp 76*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 77*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 78*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 79*264eaa0eSValentin Longchamp (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 80*264eaa0eSValentin Longchamp 81*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 82*264eaa0eSValentin Longchamp CSCONFIG_ODT_WR_CFG | \ 83*264eaa0eSValentin Longchamp CSCONFIG_ROW_BIT_13 | \ 84*264eaa0eSValentin Longchamp CSCONFIG_COL_BIT_10) 85*264eaa0eSValentin Longchamp 86*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_MODE 0x47860252 87*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_MODE2 0x8080c000 88*264eaa0eSValentin Longchamp 89*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 90*264eaa0eSValentin Longchamp (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 91*264eaa0eSValentin Longchamp (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 92*264eaa0eSValentin Longchamp (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 93*264eaa0eSValentin Longchamp (0 << TIMING_CFG0_WWT_SHIFT) | \ 94*264eaa0eSValentin Longchamp (0 << TIMING_CFG0_RRT_SHIFT) | \ 95*264eaa0eSValentin Longchamp (0 << TIMING_CFG0_WRT_SHIFT) | \ 96*264eaa0eSValentin Longchamp (0 << TIMING_CFG0_RWT_SHIFT)) 97*264eaa0eSValentin Longchamp 98*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ 99*264eaa0eSValentin Longchamp (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 100*264eaa0eSValentin Longchamp (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 101*264eaa0eSValentin Longchamp (2 << TIMING_CFG1_WRREC_SHIFT) | \ 102*264eaa0eSValentin Longchamp (6 << TIMING_CFG1_REFREC_SHIFT) | \ 103*264eaa0eSValentin Longchamp (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ 104*264eaa0eSValentin Longchamp (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 105*264eaa0eSValentin Longchamp (2 << TIMING_CFG1_PRETOACT_SHIFT)) 106*264eaa0eSValentin Longchamp 107*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 108*264eaa0eSValentin Longchamp (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 109*264eaa0eSValentin Longchamp (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 110*264eaa0eSValentin Longchamp (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 111*264eaa0eSValentin Longchamp (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 112*264eaa0eSValentin Longchamp (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 113*264eaa0eSValentin Longchamp (5 << TIMING_CFG2_CPO_SHIFT)) 114*264eaa0eSValentin Longchamp 115*264eaa0eSValentin Longchamp #define CONFIG_SYS_DDR_TIMING_3 0x00000000 116*264eaa0eSValentin Longchamp 117*264eaa0eSValentin Longchamp #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 118*264eaa0eSValentin Longchamp #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 119*264eaa0eSValentin Longchamp 120*264eaa0eSValentin Longchamp /* EEprom support */ 121*264eaa0eSValentin Longchamp #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 122*264eaa0eSValentin Longchamp 123*264eaa0eSValentin Longchamp /* 124*264eaa0eSValentin Longchamp * Local Bus Configuration & Clock Setup 125*264eaa0eSValentin Longchamp */ 126*264eaa0eSValentin Longchamp #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) 127*264eaa0eSValentin Longchamp #define CONFIG_SYS_LBC_LBCR 0x00000000 128*264eaa0eSValentin Longchamp 129*264eaa0eSValentin Longchamp /* 130*264eaa0eSValentin Longchamp * MMU Setup 131*264eaa0eSValentin Longchamp */ 132*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT7L (0) 133*264eaa0eSValentin Longchamp #define CONFIG_SYS_IBAT7U (0) 134*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 135*264eaa0eSValentin Longchamp #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 136*264eaa0eSValentin Longchamp 137*264eaa0eSValentin Longchamp #endif /* __CONFIG_KM8321_COMMON_H */ 138