1 /* 2 * Copyright (C) 2012 Keymile AG 3 * Gerlando Falauto <gerlando.falauto@keymile.com> 4 * 5 * Based on km8321-common.h, see respective copyright notice for credits 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_KM8309_COMMON_H 11 #define __CONFIG_KM8309_COMMON_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 /* E300 family */ 17 #define CONFIG_QE 1 /* Has QE */ 18 #define CONFIG_MPC830x 1 /* MPC830x family */ 19 #define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ 20 21 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 22 #define CONFIG_CMD_DIAG 1 23 24 /* include common defines/options for all 83xx Keymile boards */ 25 #include "km83xx-common.h" 26 27 /* QE microcode/firmware address */ 28 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 29 /* between the u-boot partition and env */ 30 #ifndef CONFIG_SYS_QE_FW_ADDR 31 #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 32 #endif 33 34 /* 35 * System IO Config 36 */ 37 /* 0x14000180 SICR_1 */ 38 #define CONFIG_SYS_SICRL (0 \ 39 | SICR_1_UART1_UART1RTS \ 40 | SICR_1_I2C_CKSTOP \ 41 | SICR_1_IRQ_A_IRQ \ 42 | SICR_1_IRQ_B_IRQ \ 43 | SICR_1_GPIO_A_GPIO \ 44 | SICR_1_GPIO_B_GPIO \ 45 | SICR_1_GPIO_C_GPIO \ 46 | SICR_1_GPIO_D_GPIO \ 47 | SICR_1_GPIO_E_GPIO \ 48 | SICR_1_GPIO_F_GPIO \ 49 | SICR_1_USB_A_UART2S \ 50 | SICR_1_USB_B_UART2RTS \ 51 | SICR_1_FEC1_FEC1 \ 52 | SICR_1_FEC2_FEC2 \ 53 ) 54 55 /* 0x00080400 SICR_2 */ 56 #define CONFIG_SYS_SICRH (0 \ 57 | SICR_2_FEC3_FEC3 \ 58 | SICR_2_HDLC1_A_HDLC1 \ 59 | SICR_2_ELBC_A_LA \ 60 | SICR_2_ELBC_B_LCLK \ 61 | SICR_2_HDLC2_A_HDLC2 \ 62 | SICR_2_USB_D_GPIO \ 63 | SICR_2_PCI_PCI \ 64 | SICR_2_HDLC1_B_HDLC1 \ 65 | SICR_2_HDLC1_C_HDLC1 \ 66 | SICR_2_HDLC2_B_GPIO \ 67 | SICR_2_HDLC2_C_HDLC2 \ 68 | SICR_2_QUIESCE_B \ 69 ) 70 71 /* GPR_1 */ 72 #define CONFIG_SYS_GPR1 0x50008060 73 74 #define CONFIG_SYS_GP1DIR 0x00000000 75 #define CONFIG_SYS_GP1ODR 0x00000000 76 #define CONFIG_SYS_GP2DIR 0xFF000000 77 #define CONFIG_SYS_GP2ODR 0x00000000 78 79 /* 80 * Hardware Reset Configuration Word 81 */ 82 #define CONFIG_SYS_HRCW_LOW (\ 83 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 84 HRCWL_DDR_TO_SCB_CLK_2X1 | \ 85 HRCWL_CSB_TO_CLKIN_2X1 | \ 86 HRCWL_CORE_TO_CSB_2X1 | \ 87 HRCWL_CE_PLL_VCO_DIV_2 | \ 88 HRCWL_CE_TO_PLL_1X3) 89 90 #define CONFIG_SYS_HRCW_HIGH (\ 91 HRCWH_PCI_AGENT | \ 92 HRCWH_PCI_ARBITER_DISABLE | \ 93 HRCWH_CORE_ENABLE | \ 94 HRCWH_FROM_0X00000100 | \ 95 HRCWH_BOOTSEQ_DISABLE | \ 96 HRCWH_SW_WATCHDOG_DISABLE | \ 97 HRCWH_ROM_LOC_LOCAL_16BIT | \ 98 HRCWH_BIG_ENDIAN | \ 99 HRCWH_LALE_NORMAL) 100 101 #define CONFIG_SYS_DDRCDR (\ 102 DDRCDR_EN | \ 103 DDRCDR_PZ_MAXZ | \ 104 DDRCDR_NZ_MAXZ | \ 105 DDRCDR_M_ODR) 106 107 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 108 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 109 SDRAM_CFG_32_BE | \ 110 SDRAM_CFG_SREN | \ 111 SDRAM_CFG_HSE) 112 113 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 114 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 115 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 116 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 117 118 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 119 CSCONFIG_ODT_RD_NEVER | \ 120 CSCONFIG_ODT_WR_ONLY_CURRENT | \ 121 CSCONFIG_ROW_BIT_13 | \ 122 CSCONFIG_COL_BIT_10) 123 124 #define CONFIG_SYS_DDR_MODE 0x47860242 125 #define CONFIG_SYS_DDR_MODE2 0x8080c000 126 127 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 128 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 129 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 130 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 131 (0 << TIMING_CFG0_WWT_SHIFT) | \ 132 (0 << TIMING_CFG0_RRT_SHIFT) | \ 133 (0 << TIMING_CFG0_WRT_SHIFT) | \ 134 (0 << TIMING_CFG0_RWT_SHIFT)) 135 136 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 137 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 138 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 139 (3 << TIMING_CFG1_WRREC_SHIFT) | \ 140 (7 << TIMING_CFG1_REFREC_SHIFT) | \ 141 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 142 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 143 (3 << TIMING_CFG1_PRETOACT_SHIFT)) 144 145 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 146 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 147 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 148 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 149 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 150 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 151 (5 << TIMING_CFG2_CPO_SHIFT)) 152 153 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 154 155 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 156 #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 157 158 /* EEprom support */ 159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 160 161 /* 162 * Local Bus Configuration & Clock Setup 163 */ 164 #define CONFIG_SYS_LCRR_DBYP 0x80000000 165 #define CONFIG_SYS_LCRR_EADC 0x00010000 166 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002 167 168 #define CONFIG_SYS_LBC_LBCR 0x00000000 169 170 /* 171 * MMU Setup 172 */ 173 #define CONFIG_SYS_IBAT7L (0) 174 #define CONFIG_SYS_IBAT7U (0) 175 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 176 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 177 178 #endif /* __CONFIG_KM8309_COMMON_H */ 179