1 /*
2  * Copyright (C) 2012 Keymile AG
3  *                    Gerlando Falauto <gerlando.falauto@keymile.com>
4  *
5  * Based on km8321-common.h, see respective copyright notice for credits
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_KM8309_COMMON_H
11 #define __CONFIG_KM8309_COMMON_H
12 
13 #define CONFIG_DISPLAY_BOARDINFO
14 
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_E300		1	/* E300 family */
19 #define CONFIG_QE		1	/* Has QE */
20 #define CONFIG_MPC830x		1	/* MPC830x family */
21 #define CONFIG_MPC8309		1	/* MPC8309 CPU specific */
22 
23 #define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
24 #define CONFIG_CMD_DIAG		1
25 
26 /* include common defines/options for all 83xx Keymile boards */
27 #include "km83xx-common.h"
28 
29 /* QE microcode/firmware address */
30 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
31 /* between the u-boot partition and env */
32 #ifndef CONFIG_SYS_QE_FW_ADDR
33 #define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
34 #endif
35 
36 /*
37  * System IO Config
38  */
39 /* 0x14000180 SICR_1 */
40 #define CONFIG_SYS_SICRL (0			\
41 		| SICR_1_UART1_UART1RTS		\
42 		| SICR_1_I2C_CKSTOP		\
43 		| SICR_1_IRQ_A_IRQ		\
44 		| SICR_1_IRQ_B_IRQ		\
45 		| SICR_1_GPIO_A_GPIO		\
46 		| SICR_1_GPIO_B_GPIO		\
47 		| SICR_1_GPIO_C_GPIO		\
48 		| SICR_1_GPIO_D_GPIO		\
49 		| SICR_1_GPIO_E_GPIO		\
50 		| SICR_1_GPIO_F_GPIO		\
51 		| SICR_1_USB_A_UART2S		\
52 		| SICR_1_USB_B_UART2RTS		\
53 		| SICR_1_FEC1_FEC1		\
54 		| SICR_1_FEC2_FEC2		\
55 		)
56 
57 /* 0x00080400 SICR_2 */
58 #define CONFIG_SYS_SICRH (0			\
59 		| SICR_2_FEC3_FEC3		\
60 		| SICR_2_HDLC1_A_HDLC1		\
61 		| SICR_2_ELBC_A_LA		\
62 		| SICR_2_ELBC_B_LCLK		\
63 		| SICR_2_HDLC2_A_HDLC2		\
64 		| SICR_2_USB_D_GPIO		\
65 		| SICR_2_PCI_PCI		\
66 		| SICR_2_HDLC1_B_HDLC1		\
67 		| SICR_2_HDLC1_C_HDLC1		\
68 		| SICR_2_HDLC2_B_GPIO		\
69 		| SICR_2_HDLC2_C_HDLC2		\
70 		| SICR_2_QUIESCE_B		\
71 		)
72 
73 /* GPR_1 */
74 #define CONFIG_SYS_GPR1  0x50008060
75 
76 #define CONFIG_SYS_GP1DIR 0x00000000
77 #define CONFIG_SYS_GP1ODR 0x00000000
78 #define CONFIG_SYS_GP2DIR 0xFF000000
79 #define CONFIG_SYS_GP2ODR 0x00000000
80 
81 /*
82  * Hardware Reset Configuration Word
83  */
84 #define CONFIG_SYS_HRCW_LOW (\
85 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
86 	HRCWL_DDR_TO_SCB_CLK_2X1 | \
87 	HRCWL_CSB_TO_CLKIN_2X1 | \
88 	HRCWL_CORE_TO_CSB_2X1 | \
89 	HRCWL_CE_PLL_VCO_DIV_2 | \
90 	HRCWL_CE_TO_PLL_1X3)
91 
92 #define CONFIG_SYS_HRCW_HIGH (\
93 	HRCWH_PCI_AGENT | \
94 	HRCWH_PCI_ARBITER_DISABLE | \
95 	HRCWH_CORE_ENABLE | \
96 	HRCWH_FROM_0X00000100 | \
97 	HRCWH_BOOTSEQ_DISABLE | \
98 	HRCWH_SW_WATCHDOG_DISABLE | \
99 	HRCWH_ROM_LOC_LOCAL_16BIT | \
100 	HRCWH_BIG_ENDIAN | \
101 	HRCWH_LALE_NORMAL)
102 
103 #define CONFIG_SYS_DDRCDR (\
104 	DDRCDR_EN | \
105 	DDRCDR_PZ_MAXZ | \
106 	DDRCDR_NZ_MAXZ | \
107 	DDRCDR_M_ODR)
108 
109 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
110 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
111 					 SDRAM_CFG_32_BE | \
112 					 SDRAM_CFG_SREN | \
113 					 SDRAM_CFG_HSE)
114 
115 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
116 #define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
117 #define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
118 				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
119 
120 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
121 					 CSCONFIG_ODT_RD_NEVER | \
122 					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
123 					 CSCONFIG_ROW_BIT_13 | \
124 					 CSCONFIG_COL_BIT_10)
125 
126 #define CONFIG_SYS_DDR_MODE	0x47860242
127 #define CONFIG_SYS_DDR_MODE2	0x8080c000
128 
129 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
130 				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
131 				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
132 				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
133 				 (0 << TIMING_CFG0_WWT_SHIFT) | \
134 				 (0 << TIMING_CFG0_RRT_SHIFT) | \
135 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
136 				 (0 << TIMING_CFG0_RWT_SHIFT))
137 
138 #define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
139 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
140 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
141 				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
142 				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
143 				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
144 				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
145 				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
146 
147 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
148 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
149 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
150 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
151 				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
152 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
153 				 (5 << TIMING_CFG2_CPO_SHIFT))
154 
155 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
156 
157 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
158 #define CONFIG_SYS_KMBEC_FPGA_SIZE	128
159 
160 /* EEprom support */
161 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
162 
163 /*
164  * Local Bus Configuration & Clock Setup
165  */
166 #define CONFIG_SYS_LCRR_DBYP	0x80000000
167 #define CONFIG_SYS_LCRR_EADC	0x00010000
168 #define CONFIG_SYS_LCRR_CLKDIV	0x00000002
169 
170 #define CONFIG_SYS_LBC_LBCR	0x00000000
171 
172 /*
173  * MMU Setup
174  */
175 #define CONFIG_SYS_IBAT7L	(0)
176 #define CONFIG_SYS_IBAT7U	(0)
177 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
178 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
179 
180 #endif /* __CONFIG_KM8309_COMMON_H */
181