16967840bSGerlando Falauto /* 26967840bSGerlando Falauto * Copyright (C) 2012 Keymile AG 36967840bSGerlando Falauto * Gerlando Falauto <gerlando.falauto@keymile.com> 46967840bSGerlando Falauto * 56967840bSGerlando Falauto * Based on km8321-common.h, see respective copyright notice for credits 66967840bSGerlando Falauto * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 86967840bSGerlando Falauto */ 96967840bSGerlando Falauto 106967840bSGerlando Falauto #ifndef __CONFIG_KM8309_COMMON_H 116967840bSGerlando Falauto #define __CONFIG_KM8309_COMMON_H 126967840bSGerlando Falauto 13fdfaa29eSKim Phillips #define CONFIG_DISPLAY_BOARDINFO 14fdfaa29eSKim Phillips 156967840bSGerlando Falauto /* 166967840bSGerlando Falauto * High Level Configuration Options 176967840bSGerlando Falauto */ 186967840bSGerlando Falauto #define CONFIG_E300 1 /* E300 family */ 196967840bSGerlando Falauto #define CONFIG_QE 1 /* Has QE */ 206967840bSGerlando Falauto #define CONFIG_MPC830x 1 /* MPC830x family */ 216967840bSGerlando Falauto #define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ 226967840bSGerlando Falauto 236515139bSHolger Brunck #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" 246967840bSGerlando Falauto #define CONFIG_CMD_DIAG 1 256967840bSGerlando Falauto 266967840bSGerlando Falauto /* include common defines/options for all 83xx Keymile boards */ 276967840bSGerlando Falauto #include "km83xx-common.h" 286967840bSGerlando Falauto 296967840bSGerlando Falauto /* QE microcode/firmware address */ 306967840bSGerlando Falauto #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 31*38467df5SValentin Longchamp /* between the u-boot partition and env */ 32*38467df5SValentin Longchamp #ifndef CONFIG_SYS_QE_FW_ADDR 33*38467df5SValentin Longchamp #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 34*38467df5SValentin Longchamp #endif 356967840bSGerlando Falauto 366967840bSGerlando Falauto /* 376967840bSGerlando Falauto * System IO Config 386967840bSGerlando Falauto */ 396967840bSGerlando Falauto /* 0x14000180 SICR_1 */ 406967840bSGerlando Falauto #define CONFIG_SYS_SICRL (0 \ 416967840bSGerlando Falauto | SICR_1_UART1_UART1RTS \ 426967840bSGerlando Falauto | SICR_1_I2C_CKSTOP \ 436967840bSGerlando Falauto | SICR_1_IRQ_A_IRQ \ 446967840bSGerlando Falauto | SICR_1_IRQ_B_IRQ \ 456967840bSGerlando Falauto | SICR_1_GPIO_A_GPIO \ 466967840bSGerlando Falauto | SICR_1_GPIO_B_GPIO \ 476967840bSGerlando Falauto | SICR_1_GPIO_C_GPIO \ 486967840bSGerlando Falauto | SICR_1_GPIO_D_GPIO \ 496967840bSGerlando Falauto | SICR_1_GPIO_E_GPIO \ 506967840bSGerlando Falauto | SICR_1_GPIO_F_GPIO \ 516967840bSGerlando Falauto | SICR_1_USB_A_UART2S \ 526967840bSGerlando Falauto | SICR_1_USB_B_UART2RTS \ 536967840bSGerlando Falauto | SICR_1_FEC1_FEC1 \ 546967840bSGerlando Falauto | SICR_1_FEC2_FEC2 \ 556967840bSGerlando Falauto ) 566967840bSGerlando Falauto 576967840bSGerlando Falauto /* 0x00080400 SICR_2 */ 586967840bSGerlando Falauto #define CONFIG_SYS_SICRH (0 \ 596967840bSGerlando Falauto | SICR_2_FEC3_FEC3 \ 606967840bSGerlando Falauto | SICR_2_HDLC1_A_HDLC1 \ 616967840bSGerlando Falauto | SICR_2_ELBC_A_LA \ 626967840bSGerlando Falauto | SICR_2_ELBC_B_LCLK \ 636967840bSGerlando Falauto | SICR_2_HDLC2_A_HDLC2 \ 646967840bSGerlando Falauto | SICR_2_USB_D_GPIO \ 656967840bSGerlando Falauto | SICR_2_PCI_PCI \ 666967840bSGerlando Falauto | SICR_2_HDLC1_B_HDLC1 \ 676967840bSGerlando Falauto | SICR_2_HDLC1_C_HDLC1 \ 686967840bSGerlando Falauto | SICR_2_HDLC2_B_GPIO \ 696967840bSGerlando Falauto | SICR_2_HDLC2_C_HDLC2 \ 706967840bSGerlando Falauto | SICR_2_QUIESCE_B \ 716967840bSGerlando Falauto ) 726967840bSGerlando Falauto 736967840bSGerlando Falauto /* GPR_1 */ 746967840bSGerlando Falauto #define CONFIG_SYS_GPR1 0x50008060 756967840bSGerlando Falauto 766967840bSGerlando Falauto #define CONFIG_SYS_GP1DIR 0x00000000 776967840bSGerlando Falauto #define CONFIG_SYS_GP1ODR 0x00000000 786967840bSGerlando Falauto #define CONFIG_SYS_GP2DIR 0xFF000000 796967840bSGerlando Falauto #define CONFIG_SYS_GP2ODR 0x00000000 806967840bSGerlando Falauto 816967840bSGerlando Falauto /* 826967840bSGerlando Falauto * Hardware Reset Configuration Word 836967840bSGerlando Falauto */ 846967840bSGerlando Falauto #define CONFIG_SYS_HRCW_LOW (\ 856967840bSGerlando Falauto HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 866967840bSGerlando Falauto HRCWL_DDR_TO_SCB_CLK_2X1 | \ 876967840bSGerlando Falauto HRCWL_CSB_TO_CLKIN_2X1 | \ 886967840bSGerlando Falauto HRCWL_CORE_TO_CSB_2X1 | \ 896967840bSGerlando Falauto HRCWL_CE_PLL_VCO_DIV_2 | \ 906967840bSGerlando Falauto HRCWL_CE_TO_PLL_1X3) 916967840bSGerlando Falauto 926967840bSGerlando Falauto #define CONFIG_SYS_HRCW_HIGH (\ 936967840bSGerlando Falauto HRCWH_PCI_AGENT | \ 946967840bSGerlando Falauto HRCWH_PCI_ARBITER_DISABLE | \ 956967840bSGerlando Falauto HRCWH_CORE_ENABLE | \ 966967840bSGerlando Falauto HRCWH_FROM_0X00000100 | \ 976967840bSGerlando Falauto HRCWH_BOOTSEQ_DISABLE | \ 986967840bSGerlando Falauto HRCWH_SW_WATCHDOG_DISABLE | \ 996967840bSGerlando Falauto HRCWH_ROM_LOC_LOCAL_16BIT | \ 1006967840bSGerlando Falauto HRCWH_BIG_ENDIAN | \ 1016967840bSGerlando Falauto HRCWH_LALE_NORMAL) 1026967840bSGerlando Falauto 103fd70858dSValentin Longchamp #define CONFIG_SYS_DDRCDR (\ 104fd70858dSValentin Longchamp DDRCDR_EN | \ 105fd70858dSValentin Longchamp DDRCDR_PZ_MAXZ | \ 106fd70858dSValentin Longchamp DDRCDR_NZ_MAXZ | \ 107fd70858dSValentin Longchamp DDRCDR_M_ODR) 108fd70858dSValentin Longchamp 1096967840bSGerlando Falauto #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 1106967840bSGerlando Falauto #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 1116967840bSGerlando Falauto SDRAM_CFG_32_BE | \ 1126967840bSGerlando Falauto SDRAM_CFG_SREN | \ 1136967840bSGerlando Falauto SDRAM_CFG_HSE) 1146967840bSGerlando Falauto 1156967840bSGerlando Falauto #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 1166967840bSGerlando Falauto #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 1176967840bSGerlando Falauto #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 1186967840bSGerlando Falauto (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 1196967840bSGerlando Falauto 1206967840bSGerlando Falauto #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 1216967840bSGerlando Falauto CSCONFIG_ODT_RD_NEVER | \ 1226967840bSGerlando Falauto CSCONFIG_ODT_WR_ONLY_CURRENT | \ 1236967840bSGerlando Falauto CSCONFIG_ROW_BIT_13 | \ 1246967840bSGerlando Falauto CSCONFIG_COL_BIT_10) 1256967840bSGerlando Falauto 1266967840bSGerlando Falauto #define CONFIG_SYS_DDR_MODE 0x47860242 1276967840bSGerlando Falauto #define CONFIG_SYS_DDR_MODE2 0x8080c000 1286967840bSGerlando Falauto 1296967840bSGerlando Falauto #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 1306967840bSGerlando Falauto (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 1316967840bSGerlando Falauto (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 1326967840bSGerlando Falauto (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 1336967840bSGerlando Falauto (0 << TIMING_CFG0_WWT_SHIFT) | \ 1346967840bSGerlando Falauto (0 << TIMING_CFG0_RRT_SHIFT) | \ 1356967840bSGerlando Falauto (0 << TIMING_CFG0_WRT_SHIFT) | \ 1366967840bSGerlando Falauto (0 << TIMING_CFG0_RWT_SHIFT)) 1376967840bSGerlando Falauto 1386967840bSGerlando Falauto #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 1396967840bSGerlando Falauto (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 1406967840bSGerlando Falauto (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 1416967840bSGerlando Falauto (3 << TIMING_CFG1_WRREC_SHIFT) | \ 1426967840bSGerlando Falauto (7 << TIMING_CFG1_REFREC_SHIFT) | \ 1436967840bSGerlando Falauto (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 1446967840bSGerlando Falauto (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 1456967840bSGerlando Falauto (3 << TIMING_CFG1_PRETOACT_SHIFT)) 1466967840bSGerlando Falauto 1476967840bSGerlando Falauto #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 1486967840bSGerlando Falauto (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 1496967840bSGerlando Falauto (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 1506967840bSGerlando Falauto (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 1516967840bSGerlando Falauto (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 1526967840bSGerlando Falauto (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 1536967840bSGerlando Falauto (5 << TIMING_CFG2_CPO_SHIFT)) 1546967840bSGerlando Falauto 1556967840bSGerlando Falauto #define CONFIG_SYS_DDR_TIMING_3 0x00000000 1566967840bSGerlando Falauto 1576967840bSGerlando Falauto #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 1586967840bSGerlando Falauto #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 1596967840bSGerlando Falauto 1606967840bSGerlando Falauto /* EEprom support */ 1616967840bSGerlando Falauto #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 1626967840bSGerlando Falauto 1636967840bSGerlando Falauto /* 1646967840bSGerlando Falauto * Local Bus Configuration & Clock Setup 1656967840bSGerlando Falauto */ 1666967840bSGerlando Falauto #define CONFIG_SYS_LCRR_DBYP 0x80000000 1676967840bSGerlando Falauto #define CONFIG_SYS_LCRR_EADC 0x00010000 1686967840bSGerlando Falauto #define CONFIG_SYS_LCRR_CLKDIV 0x00000002 1696967840bSGerlando Falauto 1706967840bSGerlando Falauto #define CONFIG_SYS_LBC_LBCR 0x00000000 1716967840bSGerlando Falauto 1726967840bSGerlando Falauto /* 1736967840bSGerlando Falauto * MMU Setup 1746967840bSGerlando Falauto */ 1756967840bSGerlando Falauto #define CONFIG_SYS_IBAT7L (0) 1766967840bSGerlando Falauto #define CONFIG_SYS_IBAT7U (0) 1776967840bSGerlando Falauto #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 1786967840bSGerlando Falauto #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 1796967840bSGerlando Falauto 1806967840bSGerlando Falauto #endif /* __CONFIG_KM8309_COMMON_H */ 181