1 /* 2 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 3 * Based on: 4 * U-Boot:include/configs/da850evm.h 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * Based on davinci_dvevm.h. Original Copyrights follow: 9 * 10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * Board 20 */ 21 #define CONFIG_DRIVER_TI_EMAC 22 #define CONFIG_BARIX_IPAM390 23 24 /* 25 * SoC Configuration 26 */ 27 #define CONFIG_MACH_DAVINCI_DA850_EVM 28 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 29 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 30 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 31 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 32 #define CONFIG_SYS_OSCIN_FREQ 24000000 33 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 34 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 35 #define CONFIG_SYS_TEXT_BASE 0xc1080000 36 37 /* 38 * Memory Info 39 */ 40 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 41 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 42 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 43 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 44 45 /* memtest start addr */ 46 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 47 48 /* memtest will be run on 16MB */ 49 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) 50 51 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 52 53 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 54 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 55 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 56 DAVINCI_SYSCFG_SUSPSRC_UART0 | \ 57 DAVINCI_SYSCFG_SUSPSRC_EMAC) 58 59 /* 60 * PLL configuration 61 */ 62 #define CONFIG_SYS_DV_CLKMODE 0 63 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 64 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 65 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 66 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 67 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 68 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 69 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 70 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 71 72 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 73 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 74 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 75 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 76 77 #define CONFIG_SYS_DA850_PLL0_PLLM 24 78 #define CONFIG_SYS_DA850_PLL1_PLLM 24 79 80 /* 81 * DDR2 memory configuration 82 */ 83 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 84 DV_DDR_PHY_EXT_STRBEN | \ 85 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 86 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 87 88 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 89 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 90 91 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 92 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 93 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 94 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 95 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 96 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 97 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 98 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 99 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 100 101 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 102 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 103 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 104 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 105 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 106 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 107 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 108 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 109 110 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 111 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 112 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 113 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 114 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 115 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 116 (2 << DV_DDR_SDCR_CL_SHIFT) | \ 117 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 118 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 119 120 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ 121 DAVINCI_ABCR_WSTROBE(2) | \ 122 DAVINCI_ABCR_WHOLD(0) | \ 123 DAVINCI_ABCR_RSETUP(1) | \ 124 DAVINCI_ABCR_RSTROBE(2) | \ 125 DAVINCI_ABCR_RHOLD(1) | \ 126 DAVINCI_ABCR_TA(0) | \ 127 DAVINCI_ABCR_ASIZE_8BIT) 128 129 /* 130 * Serial Driver info 131 */ 132 #define CONFIG_SYS_NS16550_SERIAL 133 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 134 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ 135 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 136 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 137 138 /* 139 * Flash & Environment 140 */ 141 #define CONFIG_NAND_DAVINCI 142 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 143 #define CONFIG_ENV_SIZE (128 << 10) 144 #define CONFIG_SYS_NAND_USE_FLASH_BBT 145 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 146 #define CONFIG_SYS_NAND_PAGE_2K 147 #define CONFIG_SYS_NAND_CS 3 148 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 149 #define CONFIG_SYS_NAND_MASK_CLE 0x10 150 #define CONFIG_SYS_NAND_MASK_ALE 0x8 151 #undef CONFIG_SYS_NAND_HW_ECC 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 153 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 154 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 155 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 156 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 157 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 158 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 159 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 160 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 161 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 162 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 163 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 164 CONFIG_SYS_MALLOC_LEN - \ 165 GENERATED_GBL_DATA_SIZE) 166 #define CONFIG_SYS_NAND_ECCPOS { \ 167 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 168 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 169 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 170 54, 55, 56, 57, 58, 59, 60, 61, 62, 63} 171 #define CONFIG_SYS_NAND_PAGE_COUNT 64 172 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 173 #define CONFIG_SYS_NAND_ECCSIZE 512 174 #define CONFIG_SYS_NAND_ECCBYTES 10 175 #define CONFIG_SYS_NAND_OOBSIZE 64 176 #define CONFIG_SPL_NAND_BASE 177 #define CONFIG_SPL_NAND_DRIVERS 178 #define CONFIG_SPL_NAND_ECC 179 #define CONFIG_SPL_NAND_SIMPLE 180 #define CONFIG_SPL_NAND_LOAD 181 182 /* 183 * Network & Ethernet Configuration 184 */ 185 #ifdef CONFIG_DRIVER_TI_EMAC 186 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 187 #define CONFIG_BOOTP_DEFAULT 188 #define CONFIG_BOOTP_DNS 189 #define CONFIG_BOOTP_DNS2 190 #define CONFIG_BOOTP_SEND_HOSTNAME 191 #define CONFIG_NET_RETRY_COUNT 10 192 #endif 193 194 /* 195 * U-Boot general configuration 196 */ 197 #define CONFIG_MISC_INIT_R 198 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 199 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 200 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 201 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 202 #define CONFIG_AUTO_COMPLETE 203 #define CONFIG_CMDLINE_EDITING 204 #define CONFIG_SYS_LONGHELP 205 #define CONFIG_MX_CYCLIC 206 207 /* 208 * Linux Information 209 */ 210 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 211 #define CONFIG_HWCONFIG /* enable hwconfig */ 212 #define CONFIG_CMDLINE_TAG 213 #define CONFIG_REVISION_TAG 214 #define CONFIG_SETUP_MEMORY_TAGS 215 #define CONFIG_EXTRA_ENV_SETTINGS \ 216 "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \ 217 "root=/dev/mtdblock5 rw noinitrd " \ 218 "rootfstype=jffs2 noinitrd\0" \ 219 "hwconfig=dsp:wake=yes\0" \ 220 "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \ 221 "bootfile=uImage\0" \ 222 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 223 "mtddevname=uboot-env\0" \ 224 "mtddevnum=0\0" \ 225 "mtdids=" MTDIDS_DEFAULT "\0" \ 226 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 227 "u-boot=/tftpboot/ipam390/u-boot.ais\0" \ 228 "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \ 229 "nand write c0000000 20000 ${filesize}\0" \ 230 "setbootparms=nand read c0100000 200000 400000;" \ 231 "run defbootargs addmtd;" \ 232 "spl export atags c0100000;" \ 233 "nand erase.part bootparms;" \ 234 "nand write c0000100 180000 20000\0" \ 235 "\0" 236 237 #ifdef CONFIG_CMD_BDI 238 #define CONFIG_CLOCKS 239 #endif 240 241 #ifndef CONFIG_DRIVER_TI_EMAC 242 #endif 243 244 #define CONFIG_MTD_DEVICE 245 #define CONFIG_MTD_PARTITIONS 246 247 #define MTDIDS_NAME_STR "davinci_nand.0" 248 #define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR 249 #define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ 250 "128k(u-boot-env)," \ 251 "1408k(u-boot)," \ 252 "128k(bootparms)," \ 253 "384k(factory-info)," \ 254 "4M(kernel)," \ 255 "-(rootfs)" 256 257 /* defines for SPL */ 258 #define CONFIG_SPL_FRAMEWORK 259 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 260 CONFIG_SYS_MALLOC_LEN) 261 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 262 #define CONFIG_SPL_STACK 0x8001ff00 263 #define CONFIG_SPL_TEXT_BASE 0x80000000 264 #define CONFIG_SPL_MAX_SIZE 0x20000 265 #define CONFIG_SPL_MAX_FOOTPRINT 32768 266 267 /* additions for new relocation code, must added to all boards */ 268 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 269 270 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 271 GENERATED_GBL_DATA_SIZE) 272 273 /* add FALCON boot mode */ 274 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 275 #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR 276 277 /* GPIO support */ 278 #define CONFIG_DA8XX_GPIO 279 #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) 280 281 #define CONFIG_SHOW_BOOT_PROGRESS 282 #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) 283 #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) 284 285 #include <asm/arch/hardware.h> 286 287 #endif /* __CONFIG_H */ 288