1 /* 2 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 3 * Based on: 4 * U-Boot:include/configs/da850evm.h 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * Based on davinci_dvevm.h. Original Copyrights follow: 9 * 10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * Board 20 */ 21 #define CONFIG_DRIVER_TI_EMAC 22 #define CONFIG_BARIX_IPAM390 23 24 /* 25 * SoC Configuration 26 */ 27 #define CONFIG_MACH_DAVINCI_DA850_EVM 28 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 29 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 30 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 31 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 32 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 33 #define CONFIG_SYS_OSCIN_FREQ 24000000 34 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 35 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 36 #define CONFIG_SYS_HZ 1000 37 #define CONFIG_SYS_DA850_PLL_INIT 38 #define CONFIG_SYS_DA850_DDR_INIT 39 #define CONFIG_SYS_TEXT_BASE 0xc1080000 40 41 /* 42 * Memory Info 43 */ 44 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 45 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 46 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 47 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 48 49 /* memtest start addr */ 50 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 51 52 /* memtest will be run on 16MB */ 53 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) 54 55 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 56 57 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 58 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 59 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 60 DAVINCI_SYSCFG_SUSPSRC_UART0 | \ 61 DAVINCI_SYSCFG_SUSPSRC_EMAC) 62 63 /* 64 * PLL configuration 65 */ 66 #define CONFIG_SYS_DV_CLKMODE 0 67 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 68 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 69 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 70 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 71 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 72 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 73 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 74 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 75 76 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 77 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 78 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 79 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 80 81 #define CONFIG_SYS_DA850_PLL0_PLLM 24 82 #define CONFIG_SYS_DA850_PLL1_PLLM 24 83 84 /* 85 * DDR2 memory configuration 86 */ 87 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 88 DV_DDR_PHY_EXT_STRBEN | \ 89 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 90 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 91 92 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 93 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 94 95 96 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 97 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 98 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 99 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 100 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 101 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 102 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 103 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 104 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 105 106 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 107 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 108 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 109 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 110 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 111 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 112 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 113 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 114 115 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 116 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 117 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 118 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 119 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 120 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 121 (2 << DV_DDR_SDCR_CL_SHIFT) | \ 122 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 123 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 124 125 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(2) | \ 126 DAVINCI_ABCR_WSTROBE(2) | \ 127 DAVINCI_ABCR_WHOLD(1) | \ 128 DAVINCI_ABCR_RSETUP(1) | \ 129 DAVINCI_ABCR_RSTROBE(4) | \ 130 DAVINCI_ABCR_RHOLD(0) | \ 131 DAVINCI_ABCR_TA(1) | \ 132 DAVINCI_ABCR_ASIZE_8BIT) 133 134 135 /* 136 * Serial Driver info 137 */ 138 #define CONFIG_SYS_NS16550 139 #define CONFIG_SYS_NS16550_SERIAL 140 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 141 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ 142 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 143 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 144 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 145 146 /* 147 * Flash & Environment 148 */ 149 #define CONFIG_NAND_DAVINCI 150 #define CONFIG_SYS_NO_FLASH 151 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ 152 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 153 #define CONFIG_ENV_SIZE (128 << 10) 154 #define CONFIG_SYS_NAND_USE_FLASH_BBT 155 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 156 #define CONFIG_SYS_NAND_PAGE_2K 157 #define CONFIG_SYS_NAND_CS 3 158 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 159 #define CONFIG_SYS_NAND_MASK_CLE 0x10 160 #define CONFIG_SYS_NAND_MASK_ALE 0x8 161 #undef CONFIG_SYS_NAND_HW_ECC 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 163 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 164 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 165 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 166 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 167 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 168 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 169 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 170 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 171 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 172 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 173 CONFIG_SYS_MALLOC_LEN - \ 174 GENERATED_GBL_DATA_SIZE) 175 #define CONFIG_SYS_NAND_ECCPOS { \ 176 24, 25, 26, 27, 28, \ 177 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 178 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 179 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 180 59, 60, 61, 62, 63 } 181 #define CONFIG_SYS_NAND_PAGE_COUNT 64 182 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 183 #define CONFIG_SYS_NAND_ECCSIZE 512 184 #define CONFIG_SYS_NAND_ECCBYTES 10 185 #define CONFIG_SYS_NAND_OOBSIZE 64 186 #define CONFIG_SPL_NAND_SUPPORT 187 #define CONFIG_SPL_NAND_BASE 188 #define CONFIG_SPL_NAND_DRIVERS 189 #define CONFIG_SPL_NAND_ECC 190 #define CONFIG_SPL_NAND_SIMPLE 191 #define CONFIG_SPL_NAND_LOAD 192 193 /* 194 * Network & Ethernet Configuration 195 */ 196 #ifdef CONFIG_DRIVER_TI_EMAC 197 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 198 #define CONFIG_BOOTP_DEFAULT 199 #define CONFIG_BOOTP_DNS 200 #define CONFIG_BOOTP_DNS2 201 #define CONFIG_BOOTP_SEND_HOSTNAME 202 #define CONFIG_NET_RETRY_COUNT 10 203 #endif 204 205 /* 206 * U-Boot general configuration 207 */ 208 #define CONFIG_MISC_INIT_R 209 #define CONFIG_BOARD_EARLY_INIT_F 210 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 211 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ 212 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 213 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 214 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 215 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 216 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 217 #define CONFIG_VERSION_VARIABLE 218 #define CONFIG_AUTO_COMPLETE 219 #define CONFIG_SYS_HUSH_PARSER 220 #define CONFIG_CMDLINE_EDITING 221 #define CONFIG_SYS_LONGHELP 222 #define CONFIG_CRC32_VERIFY 223 #define CONFIG_MX_CYCLIC 224 225 /* 226 * Linux Information 227 */ 228 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 229 #define CONFIG_HWCONFIG /* enable hwconfig */ 230 #define CONFIG_CMDLINE_TAG 231 #define CONFIG_REVISION_TAG 232 #define CONFIG_SETUP_MEMORY_TAGS 233 #define CONFIG_BOOTARGS \ 234 "mem=128M console=ttyS0,115200n8 root=/dev/mtdblock0p4 rw noinitrd ip=dhcp" 235 #define CONFIG_BOOTDELAY 3 236 #define CONFIG_EXTRA_ENV_SETTINGS \ 237 "hwconfig=dsp:wake=yes\0" \ 238 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 239 "mtdids=" MTDIDS_DEFAULT "\0" \ 240 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 241 "setbootparms=nand read c0100000 200000 400000;" \ 242 "spl export atags c0100000;" \ 243 "nand erase.part bootparms;" \ 244 "nand write c0000100 180000 20000\0" \ 245 "\0" 246 247 /* 248 * U-Boot commands 249 */ 250 #include <config_cmd_default.h> 251 #define CONFIG_CMD_ENV 252 #define CONFIG_CMD_ASKENV 253 #define CONFIG_CMD_DHCP 254 #define CONFIG_CMD_DIAG 255 #define CONFIG_CMD_MII 256 #define CONFIG_CMD_PING 257 #define CONFIG_CMD_SAVES 258 #define CONFIG_CMD_MEMORY 259 260 #ifdef CONFIG_CMD_BDI 261 #define CONFIG_CLOCKS 262 #endif 263 264 #ifndef CONFIG_DRIVER_TI_EMAC 265 #undef CONFIG_CMD_NET 266 #undef CONFIG_CMD_DHCP 267 #undef CONFIG_CMD_MII 268 #undef CONFIG_CMD_PING 269 #endif 270 271 #define CONFIG_CMD_NAND 272 #define CONFIG_CMD_NAND_TRIMFFS 273 274 #define CONFIG_CMD_MTDPARTS 275 #define CONFIG_MTD_DEVICE 276 #define CONFIG_MTD_PARTITIONS 277 #define CONFIG_LZO 278 #define CONFIG_RBTREE 279 #define CONFIG_CMD_UBI 280 #define CONFIG_CMD_UBIFS 281 282 #define MTDIDS_NAME_STR "davinci_nand.0" 283 #define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR 284 #define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ 285 "128k(u-boot-env)," \ 286 "1408k(u-boot)," \ 287 "128k(bootparms)," \ 288 "384k(factory-info)," \ 289 "4M(kernel)," \ 290 "-(rootfs)" 291 292 /* defines for SPL */ 293 #define CONFIG_SPL 294 #define CONFIG_SPL_FRAMEWORK 295 #define CONFIG_SPL_BOARD_INIT 296 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 297 CONFIG_SYS_MALLOC_LEN) 298 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 299 #define CONFIG_SPL_SERIAL_SUPPORT 300 #define CONFIG_SPL_LIBCOMMON_SUPPORT 301 #define CONFIG_SPL_LIBGENERIC_SUPPORT 302 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" 303 #define CONFIG_SPL_STACK 0x8001ff00 304 #define CONFIG_SPL_TEXT_BASE 0x80000000 305 #define CONFIG_SPL_MAX_SIZE 0x20000 306 #define CONFIG_SPL_MAX_FOOTPRINT 32768 307 308 /* additions for new relocation code, must added to all boards */ 309 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 310 311 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 312 GENERATED_GBL_DATA_SIZE) 313 314 /* add FALCON boot mode */ 315 #define CONFIG_CMD_SPL 316 #define CONFIG_SPL_OS_BOOT 317 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 318 #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR 319 #define CONFIG_CMD_SPL_NAND_OFS 0x00180000 320 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 321 322 /* GPIO support */ 323 #define CONFIG_SPL_GPIO_SUPPORT 324 #define CONFIG_DA8XX_GPIO 325 #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) 326 327 #define CONFIG_SHOW_BOOT_PROGRESS 328 #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) 329 #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) 330 331 #endif /* __CONFIG_H */ 332