1 /* 2 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 3 * Based on: 4 * U-Boot:include/configs/da850evm.h 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * Based on davinci_dvevm.h. Original Copyrights follow: 9 * 10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * Board 20 */ 21 #define CONFIG_DRIVER_TI_EMAC 22 #define CONFIG_BARIX_IPAM390 23 24 /* 25 * SoC Configuration 26 */ 27 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 28 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 29 #define CONFIG_SYS_OSCIN_FREQ 24000000 30 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 31 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 32 33 /* 34 * Memory Info 35 */ 36 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 37 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 38 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 39 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 40 41 /* memtest start addr */ 42 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 43 44 /* memtest will be run on 16MB */ 45 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) 46 47 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 48 49 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 50 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 51 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 52 DAVINCI_SYSCFG_SUSPSRC_UART0 | \ 53 DAVINCI_SYSCFG_SUSPSRC_EMAC) 54 55 /* 56 * PLL configuration 57 */ 58 59 #define CONFIG_SYS_DA850_PLL0_PLLM 24 60 #define CONFIG_SYS_DA850_PLL1_PLLM 24 61 62 /* 63 * DDR2 memory configuration 64 */ 65 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 66 DV_DDR_PHY_EXT_STRBEN | \ 67 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 68 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 69 70 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 71 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 72 73 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 74 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 75 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 76 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 77 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 78 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 79 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 80 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 81 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 82 83 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 84 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 85 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 86 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 87 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 88 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 89 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 90 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 91 92 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 93 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 94 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 95 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 96 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 97 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 98 (2 << DV_DDR_SDCR_CL_SHIFT) | \ 99 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 100 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 101 102 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ 103 DAVINCI_ABCR_WSTROBE(2) | \ 104 DAVINCI_ABCR_WHOLD(0) | \ 105 DAVINCI_ABCR_RSETUP(1) | \ 106 DAVINCI_ABCR_RSTROBE(2) | \ 107 DAVINCI_ABCR_RHOLD(1) | \ 108 DAVINCI_ABCR_TA(0) | \ 109 DAVINCI_ABCR_ASIZE_8BIT) 110 111 /* 112 * Serial Driver info 113 */ 114 #define CONFIG_SYS_NS16550_SERIAL 115 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 116 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ 117 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 118 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 119 120 /* 121 * Flash & Environment 122 */ 123 #define CONFIG_NAND_DAVINCI 124 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 125 #define CONFIG_ENV_SIZE (128 << 10) 126 #define CONFIG_SYS_NAND_USE_FLASH_BBT 127 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 128 #define CONFIG_SYS_NAND_PAGE_2K 129 #define CONFIG_SYS_NAND_CS 3 130 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 131 #define CONFIG_SYS_NAND_MASK_CLE 0x10 132 #define CONFIG_SYS_NAND_MASK_ALE 0x8 133 #undef CONFIG_SYS_NAND_HW_ECC 134 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 135 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 136 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 137 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 138 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 139 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 140 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 141 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 142 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 143 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 144 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 145 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 146 CONFIG_SYS_MALLOC_LEN - \ 147 GENERATED_GBL_DATA_SIZE) 148 #define CONFIG_SYS_NAND_ECCPOS { \ 149 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 150 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 151 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 152 54, 55, 56, 57, 58, 59, 60, 61, 62, 63} 153 #define CONFIG_SYS_NAND_PAGE_COUNT 64 154 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 155 #define CONFIG_SYS_NAND_ECCSIZE 512 156 #define CONFIG_SYS_NAND_ECCBYTES 10 157 #define CONFIG_SYS_NAND_OOBSIZE 64 158 #define CONFIG_SPL_NAND_BASE 159 #define CONFIG_SPL_NAND_DRIVERS 160 #define CONFIG_SPL_NAND_ECC 161 #define CONFIG_SPL_NAND_LOAD 162 163 /* 164 * Network & Ethernet Configuration 165 */ 166 #ifdef CONFIG_DRIVER_TI_EMAC 167 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 168 #define CONFIG_BOOTP_DEFAULT 169 #define CONFIG_BOOTP_DNS 170 #define CONFIG_BOOTP_DNS2 171 #define CONFIG_BOOTP_SEND_HOSTNAME 172 #define CONFIG_NET_RETRY_COUNT 10 173 #endif 174 175 /* 176 * U-Boot general configuration 177 */ 178 #define CONFIG_MISC_INIT_R 179 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 180 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 181 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 182 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 183 #define CONFIG_AUTO_COMPLETE 184 #define CONFIG_CMDLINE_EDITING 185 #define CONFIG_SYS_LONGHELP 186 #define CONFIG_MX_CYCLIC 187 188 /* 189 * Linux Information 190 */ 191 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 192 #define CONFIG_HWCONFIG /* enable hwconfig */ 193 #define CONFIG_CMDLINE_TAG 194 #define CONFIG_REVISION_TAG 195 #define CONFIG_SETUP_MEMORY_TAGS 196 #define CONFIG_EXTRA_ENV_SETTINGS \ 197 "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \ 198 "root=/dev/mtdblock5 rw noinitrd " \ 199 "rootfstype=jffs2 noinitrd\0" \ 200 "hwconfig=dsp:wake=yes\0" \ 201 "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \ 202 "bootfile=uImage\0" \ 203 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 204 "mtddevname=uboot-env\0" \ 205 "mtddevnum=0\0" \ 206 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 207 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 208 "u-boot=/tftpboot/ipam390/u-boot.ais\0" \ 209 "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \ 210 "nand write c0000000 20000 ${filesize}\0" \ 211 "setbootparms=nand read c0100000 200000 400000;" \ 212 "run defbootargs addmtd;" \ 213 "spl export atags c0100000;" \ 214 "nand erase.part bootparms;" \ 215 "nand write c0000100 180000 20000\0" \ 216 "\0" 217 218 #ifdef CONFIG_CMD_BDI 219 #define CONFIG_CLOCKS 220 #endif 221 222 #ifndef CONFIG_DRIVER_TI_EMAC 223 #endif 224 225 #define CONFIG_MTD_DEVICE 226 #define CONFIG_MTD_PARTITIONS 227 228 /* defines for SPL */ 229 #define CONFIG_SPL_FRAMEWORK 230 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 231 CONFIG_SYS_MALLOC_LEN) 232 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 233 #define CONFIG_SPL_STACK 0x8001ff00 234 #define CONFIG_SPL_TEXT_BASE 0x80000000 235 #define CONFIG_SPL_MAX_SIZE 0x20000 236 #define CONFIG_SPL_MAX_FOOTPRINT 32768 237 238 /* additions for new relocation code, must added to all boards */ 239 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 240 241 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 242 GENERATED_GBL_DATA_SIZE) 243 244 /* add FALCON boot mode */ 245 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 246 #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR 247 248 /* GPIO support */ 249 #define CONFIG_DA8XX_GPIO 250 #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) 251 252 #define CONFIG_SHOW_BOOT_PROGRESS 253 #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) 254 #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) 255 256 #include <asm/arch/hardware.h> 257 258 #endif /* __CONFIG_H */ 259