1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * Based on: 5 * U-Boot:include/configs/da850evm.h 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 8 * 9 * Based on davinci_dvevm.h. Original Copyrights follow: 10 * 11 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* 18 * Board 19 */ 20 #define CONFIG_DRIVER_TI_EMAC 21 22 /* 23 * SoC Configuration 24 */ 25 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 26 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 27 #define CONFIG_SYS_OSCIN_FREQ 24000000 28 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 29 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 30 31 /* 32 * Memory Info 33 */ 34 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 35 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 36 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 37 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 38 39 /* memtest start addr */ 40 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 41 42 /* memtest will be run on 16MB */ 43 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) 44 45 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 46 47 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 48 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 49 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 50 DAVINCI_SYSCFG_SUSPSRC_UART0 | \ 51 DAVINCI_SYSCFG_SUSPSRC_EMAC) 52 53 /* 54 * PLL configuration 55 */ 56 57 #define CONFIG_SYS_DA850_PLL0_PLLM 24 58 #define CONFIG_SYS_DA850_PLL1_PLLM 24 59 60 /* 61 * DDR2 memory configuration 62 */ 63 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 64 DV_DDR_PHY_EXT_STRBEN | \ 65 (0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 66 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 67 68 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 69 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 70 71 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 72 (13 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 73 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 74 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 75 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ 76 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 77 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 78 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 79 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 80 81 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 82 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 83 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 84 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 85 (14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 86 (0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 87 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 88 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 89 90 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 91 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 92 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 93 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 94 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 95 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 96 (2 << DV_DDR_SDCR_CL_SHIFT) | \ 97 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 98 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 99 100 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ 101 DAVINCI_ABCR_WSTROBE(2) | \ 102 DAVINCI_ABCR_WHOLD(0) | \ 103 DAVINCI_ABCR_RSETUP(1) | \ 104 DAVINCI_ABCR_RSTROBE(2) | \ 105 DAVINCI_ABCR_RHOLD(1) | \ 106 DAVINCI_ABCR_TA(0) | \ 107 DAVINCI_ABCR_ASIZE_8BIT) 108 109 /* 110 * Serial Driver info 111 */ 112 #define CONFIG_SYS_NS16550_SERIAL 113 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 114 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ 115 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 116 117 /* 118 * Flash & Environment 119 */ 120 #define CONFIG_NAND_DAVINCI 121 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ 122 #define CONFIG_ENV_SIZE (128 << 10) 123 #define CONFIG_SYS_NAND_USE_FLASH_BBT 124 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 125 #define CONFIG_SYS_NAND_PAGE_2K 126 #define CONFIG_SYS_NAND_CS 3 127 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 128 #define CONFIG_SYS_NAND_MASK_CLE 0x10 129 #define CONFIG_SYS_NAND_MASK_ALE 0x8 130 #undef CONFIG_SYS_NAND_HW_ECC 131 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 132 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 133 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 134 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 135 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) 136 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) 137 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 138 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 139 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 140 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 141 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ 142 CONFIG_SYS_NAND_U_BOOT_SIZE - \ 143 CONFIG_SYS_MALLOC_LEN - \ 144 GENERATED_GBL_DATA_SIZE) 145 #define CONFIG_SYS_NAND_ECCPOS { \ 146 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 147 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 148 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 149 54, 55, 56, 57, 58, 59, 60, 61, 62, 63} 150 #define CONFIG_SYS_NAND_PAGE_COUNT 64 151 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 152 #define CONFIG_SYS_NAND_ECCSIZE 512 153 #define CONFIG_SYS_NAND_ECCBYTES 10 154 #define CONFIG_SYS_NAND_OOBSIZE 64 155 #define CONFIG_SPL_NAND_BASE 156 #define CONFIG_SPL_NAND_DRIVERS 157 #define CONFIG_SPL_NAND_ECC 158 #define CONFIG_SPL_NAND_LOAD 159 160 /* 161 * Network & Ethernet Configuration 162 */ 163 #ifdef CONFIG_DRIVER_TI_EMAC 164 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 165 #define CONFIG_BOOTP_DEFAULT 166 #define CONFIG_BOOTP_DNS2 167 #define CONFIG_BOOTP_SEND_HOSTNAME 168 #define CONFIG_NET_RETRY_COUNT 10 169 #endif 170 171 /* 172 * U-Boot general configuration 173 */ 174 #define CONFIG_MISC_INIT_R 175 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 176 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 177 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 178 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 179 #define CONFIG_MX_CYCLIC 180 181 /* 182 * Linux Information 183 */ 184 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 185 #define CONFIG_HWCONFIG /* enable hwconfig */ 186 #define CONFIG_CMDLINE_TAG 187 #define CONFIG_REVISION_TAG 188 #define CONFIG_SETUP_MEMORY_TAGS 189 #define CONFIG_EXTRA_ENV_SETTINGS \ 190 "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \ 191 "root=/dev/mtdblock5 rw noinitrd " \ 192 "rootfstype=jffs2 noinitrd\0" \ 193 "hwconfig=dsp:wake=yes\0" \ 194 "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \ 195 "bootfile=uImage\0" \ 196 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 197 "mtddevname=uboot-env\0" \ 198 "mtddevnum=0\0" \ 199 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 200 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 201 "u-boot=/tftpboot/ipam390/u-boot.ais\0" \ 202 "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \ 203 "nand write c0000000 20000 ${filesize}\0" \ 204 "setbootparms=nand read c0100000 200000 400000;" \ 205 "run defbootargs addmtd;" \ 206 "spl export atags c0100000;" \ 207 "nand erase.part bootparms;" \ 208 "nand write c0000100 180000 20000\0" \ 209 "\0" 210 211 #ifdef CONFIG_CMD_BDI 212 #define CONFIG_CLOCKS 213 #endif 214 215 #ifndef CONFIG_DRIVER_TI_EMAC 216 #endif 217 218 #define CONFIG_MTD_DEVICE 219 #define CONFIG_MTD_PARTITIONS 220 221 /* defines for SPL */ 222 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ 223 CONFIG_SYS_MALLOC_LEN) 224 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 225 #define CONFIG_SPL_STACK 0x8001ff00 226 #define CONFIG_SPL_TEXT_BASE 0x80000000 227 #define CONFIG_SPL_MAX_SIZE 0x20000 228 #define CONFIG_SPL_MAX_FOOTPRINT 32768 229 230 /* additions for new relocation code, must added to all boards */ 231 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 232 233 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 234 GENERATED_GBL_DATA_SIZE) 235 236 /* add FALCON boot mode */ 237 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 238 #define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR 239 240 /* GPIO support */ 241 #define CONFIG_DA8XX_GPIO 242 #define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) 243 244 #define CONFIG_SHOW_BOOT_PROGRESS 245 #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) 246 #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) 247 248 #include <asm/arch/hardware.h> 249 250 #endif /* __CONFIG_H */ 251