1 /* 2 * (C) Copyright 2003 3 * Texas Instruments. 4 * Kshitij Gupta <kshitij@ti.com> 5 * Configuation settings for the TI OMAP Innovator board. 6 * 7 * (C) Copyright 2004 8 * ARM Ltd. 9 * Philippe Robin, <philippe.robin@arm.com> 10 * Configuration for Integrator AP board. 11 *. 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_SYS_MEMTEST_START 0x100000 38 #define CONFIG_SYS_MEMTEST_END 0x10000000 39 #define CONFIG_SYS_HZ 1000 40 #define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ 41 #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ 42 43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 1 45 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ 46 47 #define CONFIG_SKIP_LOWLEVEL_INIT 48 #define CONFIG_CM_INIT 1 49 #define CONFIG_CM_REMAP 1 50 #undef CONFIG_CM_SPD_DETECT 51 52 /* 53 * Size of malloc() pool 54 */ 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 56 57 /* 58 * PL010 Configuration 59 */ 60 #define CONFIG_PL010_SERIAL 61 #define CONFIG_CONS_INDEX 0 62 #define CONFIG_BAUDRATE 38400 63 #define CONFIG_PL01x_PORTS { (void *) (CONFIG_SYS_SERIAL0), (void *) (CONFIG_SYS_SERIAL1) } 64 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 65 #define CONFIG_SYS_SERIAL0 0x16000000 66 #define CONFIG_SYS_SERIAL1 0x17000000 67 68 /*#define CONFIG_NET_MULTI */ 69 70 71 /* 72 * BOOTP options 73 */ 74 #define CONFIG_BOOTP_BOOTFILESIZE 75 #define CONFIG_BOOTP_BOOTPATH 76 #define CONFIG_BOOTP_GATEWAY 77 #define CONFIG_BOOTP_HOSTNAME 78 79 80 /* 81 * Command line configuration. 82 */ 83 84 #define CONFIG_CMD_IMI 85 #define CONFIG_CMD_BDI 86 #define CONFIG_CMD_MEMORY 87 88 89 #define CONFIG_BOOTDELAY 2 90 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" 91 #define CONFIG_BOOTCOMMAND "" 92 93 /* 94 * Miscellaneous configurable options 95 */ 96 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 97 #define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ 98 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 99 /* Print Buffer Size */ 100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 101 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 102 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 103 104 #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ 105 106 /*----------------------------------------------------------------------- 107 * Stack sizes 108 * 109 * The stack sizes are set up in start.S using the settings below 110 */ 111 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ 112 #ifdef CONFIG_USE_IRQ 113 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 114 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 115 #endif 116 117 /*----------------------------------------------------------------------- 118 * Physical Memory Map 119 */ 120 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 121 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ 122 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 123 124 #define CONFIG_SYS_FLASH_BASE 0x24000000 125 126 /*----------------------------------------------------------------------- 127 * FLASH and environment organization 128 */ 129 #define CONFIG_SYS_FLASH_CFI 1 130 #define CONFIG_FLASH_CFI_DRIVER 1 131 #define CONFIG_ENV_IS_NOWHERE 132 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 133 /* timeout values are in ticks */ 134 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 135 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 136 #define CONFIG_SYS_MAX_FLASH_SECT 128 137 #define CONFIG_ENV_SIZE 32768 138 139 140 /*----------------------------------------------------------------------- 141 * PCI definitions 142 */ 143 144 #ifdef CONFIG_PCI /* pci support */ 145 #undef CONFIG_PCI_PNP 146 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 147 #define DEBUG 148 149 #define CONFIG_EEPRO100 150 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 151 152 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 153 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 154 155 /* PCI Base area */ 156 #define INTEGRATOR_PCI_BASE 0x40000000 157 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF 158 159 /* memory map as seen by the CPU on the local bus */ 160 #define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ 161 #define CPU_PCI_IO_SIZE 0x10000 162 163 #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ 164 #define CPU_PCI_CNFG_SIZE 0x1000000 165 166 #define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ 167 /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ 168 #define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ 169 /* unused (128-16)M from B1000000-B7FFFFFF */ 170 #define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ 171 /* unused ((128-16)M - 64K) from XXX */ 172 173 #define PCI_V3_BASE 0x62000000 174 175 /* V3 PCI bridge controller */ 176 #define V3_BASE 0x62000000 /* V360EPC registers */ 177 178 #define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) 179 #define PCI_ENET0_MEMADDR (PCI_MEM_BASE) 180 181 182 #define V3_PCI_VENDOR 0x00000000 183 #define V3_PCI_DEVICE 0x00000002 184 #define V3_PCI_CMD 0x00000004 185 #define V3_PCI_STAT 0x00000006 186 #define V3_PCI_CC_REV 0x00000008 187 #define V3_PCI_HDR_CF 0x0000000C 188 #define V3_PCI_IO_BASE 0x00000010 189 #define V3_PCI_BASE0 0x00000014 190 #define V3_PCI_BASE1 0x00000018 191 #define V3_PCI_SUB_VENDOR 0x0000002C 192 #define V3_PCI_SUB_ID 0x0000002E 193 #define V3_PCI_ROM 0x00000030 194 #define V3_PCI_BPARAM 0x0000003C 195 #define V3_PCI_MAP0 0x00000040 196 #define V3_PCI_MAP1 0x00000044 197 #define V3_PCI_INT_STAT 0x00000048 198 #define V3_PCI_INT_CFG 0x0000004C 199 #define V3_LB_BASE0 0x00000054 200 #define V3_LB_BASE1 0x00000058 201 #define V3_LB_MAP0 0x0000005E 202 #define V3_LB_MAP1 0x00000062 203 #define V3_LB_BASE2 0x00000064 204 #define V3_LB_MAP2 0x00000066 205 #define V3_LB_SIZE 0x00000068 206 #define V3_LB_IO_BASE 0x0000006E 207 #define V3_FIFO_CFG 0x00000070 208 #define V3_FIFO_PRIORITY 0x00000072 209 #define V3_FIFO_STAT 0x00000074 210 #define V3_LB_ISTAT 0x00000076 211 #define V3_LB_IMASK 0x00000077 212 #define V3_SYSTEM 0x00000078 213 #define V3_LB_CFG 0x0000007A 214 #define V3_PCI_CFG 0x0000007C 215 #define V3_DMA_PCI_ADR0 0x00000080 216 #define V3_DMA_PCI_ADR1 0x00000090 217 #define V3_DMA_LOCAL_ADR0 0x00000084 218 #define V3_DMA_LOCAL_ADR1 0x00000094 219 #define V3_DMA_LENGTH0 0x00000088 220 #define V3_DMA_LENGTH1 0x00000098 221 #define V3_DMA_CSR0 0x0000008B 222 #define V3_DMA_CSR1 0x0000009B 223 #define V3_DMA_CTLB_ADR0 0x0000008C 224 #define V3_DMA_CTLB_ADR1 0x0000009C 225 #define V3_DMA_DELAY 0x000000E0 226 #define V3_MAIL_DATA 0x000000C0 227 #define V3_PCI_MAIL_IEWR 0x000000D0 228 #define V3_PCI_MAIL_IERD 0x000000D2 229 #define V3_LB_MAIL_IEWR 0x000000D4 230 #define V3_LB_MAIL_IERD 0x000000D6 231 #define V3_MAIL_WR_STAT 0x000000D8 232 #define V3_MAIL_RD_STAT 0x000000DA 233 #define V3_QBA_MAP 0x000000DC 234 235 /* SYSTEM register bits */ 236 #define V3_SYSTEM_M_RST_OUT (1 << 15) 237 #define V3_SYSTEM_M_LOCK (1 << 14) 238 239 /* PCI_CFG bits */ 240 #define V3_PCI_CFG_M_RETRY_EN (1 << 10) 241 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9) 242 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8) 243 244 /* PCI MAP register bits (PCI -> Local bus) */ 245 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 246 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15) 247 #define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) 248 #define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) 249 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 250 #define V3_PCI_MAP_M_REG_EN (1 << 1) 251 #define V3_PCI_MAP_M_ENABLE (1 << 0) 252 253 /* 9 => 512M window size */ 254 #define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 255 256 /* A => 1024M window size */ 257 #define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 258 259 /* LB_BASE register bits (Local bus -> PCI) */ 260 #define V3_LB_BASE_M_MAP_ADR 0xFFF00000 261 #define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) 262 #define V3_LB_BASE_M_ADR_SIZE 0x000000F0 263 #define V3_LB_BASE_M_PREFETCH (1 << 3) 264 #define V3_LB_BASE_M_ENABLE (1 << 0) 265 266 /* PCI COMMAND REGISTER bits */ 267 #define V3_COMMAND_M_FBB_EN (1 << 9) 268 #define V3_COMMAND_M_SERR_EN (1 << 8) 269 #define V3_COMMAND_M_PAR_EN (1 << 6) 270 #define V3_COMMAND_M_MASTER_EN (1 << 2) 271 #define V3_COMMAND_M_MEM_EN (1 << 1) 272 #define V3_COMMAND_M_IO_EN (1 << 0) 273 274 #define INTEGRATOR_SC_BASE 0x11000000 275 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 276 #define INTEGRATOR_SC_PCIENABLE \ 277 (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) 278 279 #endif /* CONFIG_PCI */ 280 /*----------------------------------------------------------------------- 281 * There are various dependencies on the core module (CM) fitted 282 * Users should refer to their CM user guide 283 * - when porting adjust u-boot/Makefile accordingly 284 * to define the necessary CONFIG_ s for the CM involved 285 * see e.g. integratorcp_CM926EJ-S_config 286 */ 287 #include "armcoremodule.h" 288 289 #endif /* __CONFIG_H */ 290