1 /* 2 * (C) Copyright 2003 3 * Texas Instruments. 4 * Kshitij Gupta <kshitij@ti.com> 5 * Configuation settings for the TI OMAP Innovator board. 6 * 7 * (C) Copyright 2004 8 * ARM Ltd. 9 * Philippe Robin, <philippe.robin@arm.com> 10 * Configuration for Integrator AP board. 11 *. 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CFG_MEMTEST_START 0x100000 38 #define CFG_MEMTEST_END 0x10000000 39 #define CFG_HZ 1000 40 #define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ 41 #define CFG_TIMERBASE 0x13000100 /* Timer1 */ 42 43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 44 #define CONFIG_SETUP_MEMORY_TAGS 1 45 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ 46 47 #undef CONFIG_INIT_CRITICAL 48 #define CONFIG_CM_INIT 1 49 #define CONFIG_CM_REMAP 1 50 #undef CONFIG_CM_SPD_DETECT 51 52 /* 53 * Size of malloc() pool 54 */ 55 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) 56 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 57 58 /* 59 * PL010 Configuration 60 */ 61 #define CONFIG_PL010_SERIAL 62 #define CONFIG_CONS_INDEX 0 63 #define CONFIG_BAUDRATE 38400 64 #define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } 65 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 66 #define CFG_SERIAL0 0x16000000 67 #define CFG_SERIAL1 0x17000000 68 69 /*#define CONFIG_NET_MULTI */ 70 71 72 /* 73 * BOOTP options 74 */ 75 #define CONFIG_BOOTP_BOOTFILESIZE 76 #define CONFIG_BOOTP_BOOTPATH 77 #define CONFIG_BOOTP_GATEWAY 78 #define CONFIG_BOOTP_HOSTNAME 79 80 81 /* 82 * Command line configuration. 83 */ 84 85 #define CONFIG_CMD_IMI 86 #define CONFIG_CMD_BDI 87 #define CONFIG_CMD_MEMORY 88 89 90 #define CONFIG_BOOTDELAY 2 91 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" 92 #define CONFIG_BOOTCOMMAND "" 93 94 /* 95 * Miscellaneous configurable options 96 */ 97 #define CFG_LONGHELP /* undef to save memory */ 98 #define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ 99 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 100 /* Print Buffer Size */ 101 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) 102 #define CFG_MAXARGS 16 /* max number of command args */ 103 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 104 105 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ 106 #define CFG_LOAD_ADDR 0x7fc0 /* default load address */ 107 108 /*----------------------------------------------------------------------- 109 * Stack sizes 110 * 111 * The stack sizes are set up in start.S using the settings below 112 */ 113 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ 114 #ifdef CONFIG_USE_IRQ 115 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 116 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 117 #endif 118 119 /*----------------------------------------------------------------------- 120 * Physical Memory Map 121 */ 122 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 123 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ 124 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 125 126 #define CFG_FLASH_BASE 0x24000000 127 128 /*----------------------------------------------------------------------- 129 * FLASH and environment organization 130 */ 131 #define CONFIG_ENV_IS_NOWHERE 132 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 133 #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ 134 /* timeout values are in ticks */ 135 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ 136 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ 137 #define CFG_MAX_FLASH_SECT 128 138 #define CFG_ENV_SIZE 32768 139 140 #define PHYS_FLASH_1 (CFG_FLASH_BASE) 141 142 /*----------------------------------------------------------------------- 143 * PCI definitions 144 */ 145 146 /*#define CONFIG_PCI /--* include pci support */ 147 #undef CONFIG_PCI_PNP 148 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 149 #define DEBUG 150 151 #define CONFIG_EEPRO100 152 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 153 154 155 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 156 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 157 158 /* PCI Base area */ 159 #define INTEGRATOR_PCI_BASE 0x40000000 160 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF 161 162 /* memory map as seen by the CPU on the local bus */ 163 #define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ 164 #define CPU_PCI_IO_SIZE 0x10000 165 166 #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ 167 #define CPU_PCI_CNFG_SIZE 0x1000000 168 169 #define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ 170 /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ 171 #define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ 172 /* unused (128-16)M from B1000000-B7FFFFFF */ 173 #define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ 174 /* unused ((128-16)M - 64K) from XXX */ 175 176 #define PCI_V3_BASE 0x62000000 177 178 /* V3 PCI bridge controller */ 179 #define V3_BASE 0x62000000 /* V360EPC registers */ 180 181 #define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) 182 #define PCI_ENET0_MEMADDR (PCI_MEM_BASE) 183 184 185 #define V3_PCI_VENDOR 0x00000000 186 #define V3_PCI_DEVICE 0x00000002 187 #define V3_PCI_CMD 0x00000004 188 #define V3_PCI_STAT 0x00000006 189 #define V3_PCI_CC_REV 0x00000008 190 #define V3_PCI_HDR_CF 0x0000000C 191 #define V3_PCI_IO_BASE 0x00000010 192 #define V3_PCI_BASE0 0x00000014 193 #define V3_PCI_BASE1 0x00000018 194 #define V3_PCI_SUB_VENDOR 0x0000002C 195 #define V3_PCI_SUB_ID 0x0000002E 196 #define V3_PCI_ROM 0x00000030 197 #define V3_PCI_BPARAM 0x0000003C 198 #define V3_PCI_MAP0 0x00000040 199 #define V3_PCI_MAP1 0x00000044 200 #define V3_PCI_INT_STAT 0x00000048 201 #define V3_PCI_INT_CFG 0x0000004C 202 #define V3_LB_BASE0 0x00000054 203 #define V3_LB_BASE1 0x00000058 204 #define V3_LB_MAP0 0x0000005E 205 #define V3_LB_MAP1 0x00000062 206 #define V3_LB_BASE2 0x00000064 207 #define V3_LB_MAP2 0x00000066 208 #define V3_LB_SIZE 0x00000068 209 #define V3_LB_IO_BASE 0x0000006E 210 #define V3_FIFO_CFG 0x00000070 211 #define V3_FIFO_PRIORITY 0x00000072 212 #define V3_FIFO_STAT 0x00000074 213 #define V3_LB_ISTAT 0x00000076 214 #define V3_LB_IMASK 0x00000077 215 #define V3_SYSTEM 0x00000078 216 #define V3_LB_CFG 0x0000007A 217 #define V3_PCI_CFG 0x0000007C 218 #define V3_DMA_PCI_ADR0 0x00000080 219 #define V3_DMA_PCI_ADR1 0x00000090 220 #define V3_DMA_LOCAL_ADR0 0x00000084 221 #define V3_DMA_LOCAL_ADR1 0x00000094 222 #define V3_DMA_LENGTH0 0x00000088 223 #define V3_DMA_LENGTH1 0x00000098 224 #define V3_DMA_CSR0 0x0000008B 225 #define V3_DMA_CSR1 0x0000009B 226 #define V3_DMA_CTLB_ADR0 0x0000008C 227 #define V3_DMA_CTLB_ADR1 0x0000009C 228 #define V3_DMA_DELAY 0x000000E0 229 #define V3_MAIL_DATA 0x000000C0 230 #define V3_PCI_MAIL_IEWR 0x000000D0 231 #define V3_PCI_MAIL_IERD 0x000000D2 232 #define V3_LB_MAIL_IEWR 0x000000D4 233 #define V3_LB_MAIL_IERD 0x000000D6 234 #define V3_MAIL_WR_STAT 0x000000D8 235 #define V3_MAIL_RD_STAT 0x000000DA 236 #define V3_QBA_MAP 0x000000DC 237 238 /* SYSTEM register bits */ 239 #define V3_SYSTEM_M_RST_OUT (1 << 15) 240 #define V3_SYSTEM_M_LOCK (1 << 14) 241 242 /* PCI_CFG bits */ 243 #define V3_PCI_CFG_M_RETRY_EN (1 << 10) 244 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9) 245 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8) 246 247 /* PCI MAP register bits (PCI -> Local bus) */ 248 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 249 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15) 250 #define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) 251 #define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) 252 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 253 #define V3_PCI_MAP_M_REG_EN (1 << 1) 254 #define V3_PCI_MAP_M_ENABLE (1 << 0) 255 256 /* 9 => 512M window size */ 257 #define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 258 259 /* A => 1024M window size */ 260 #define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 261 262 /* LB_BASE register bits (Local bus -> PCI) */ 263 #define V3_LB_BASE_M_MAP_ADR 0xFFF00000 264 #define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) 265 #define V3_LB_BASE_M_ADR_SIZE 0x000000F0 266 #define V3_LB_BASE_M_PREFETCH (1 << 3) 267 #define V3_LB_BASE_M_ENABLE (1 << 0) 268 269 /* PCI COMMAND REGISTER bits */ 270 #define V3_COMMAND_M_FBB_EN (1 << 9) 271 #define V3_COMMAND_M_SERR_EN (1 << 8) 272 #define V3_COMMAND_M_PAR_EN (1 << 6) 273 #define V3_COMMAND_M_MASTER_EN (1 << 2) 274 #define V3_COMMAND_M_MEM_EN (1 << 1) 275 #define V3_COMMAND_M_IO_EN (1 << 0) 276 277 #define INTEGRATOR_SC_BASE 0x11000000 278 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 279 #define INTEGRATOR_SC_PCIENABLE \ 280 (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) 281 282 /*----------------------------------------------------------------------- 283 * There are various dependencies on the core module (CM) fitted 284 * Users should refer to their CM user guide 285 * - when porting adjust u-boot/Makefile accordingly 286 * to define the necessary CONFIG_ s for the CM involved 287 * see e.g. integratorcp_CM926EJ-S_config 288 */ 289 #include "armcoremodule.h" 290 291 #endif /* __CONFIG_H */ 292