1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e62b008fSLinus Walleij /* 3e62b008fSLinus Walleij * (C) Copyright 2012 4e62b008fSLinus Walleij * Linaro 5e62b008fSLinus Walleij * Linus Walleij <linus.walleij@linaro.org> 6e62b008fSLinus Walleij * Common ARM Integrator configuration settings 7e62b008fSLinus Walleij */ 8e62b008fSLinus Walleij 9e62b008fSLinus Walleij #define CONFIG_SYS_MEMTEST_START 0x100000 10e62b008fSLinus Walleij #define CONFIG_SYS_MEMTEST_END 0x10000000 11e62b008fSLinus Walleij #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ 12e62b008fSLinus Walleij #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ 13e62b008fSLinus Walleij #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ 14e62b008fSLinus Walleij 15e62b008fSLinus Walleij #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 16e62b008fSLinus Walleij #define CONFIG_SETUP_MEMORY_TAGS 17e62b008fSLinus Walleij 18e62b008fSLinus Walleij /* 19e62b008fSLinus Walleij * There are various dependencies on the core module (CM) fitted 20e62b008fSLinus Walleij * Users should refer to their CM user guide 21e62b008fSLinus Walleij */ 22e62b008fSLinus Walleij #include "armcoremodule.h" 23e62b008fSLinus Walleij 24e62b008fSLinus Walleij /* 25e62b008fSLinus Walleij * Initialize and remap the core module, use SPD to detect memory size 26e62b008fSLinus Walleij * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & 27e62b008fSLinus Walleij * the core module has a CM_INIT register 28e62b008fSLinus Walleij * then the U-Boot initialisation code will 29e62b008fSLinus Walleij * e.g. ARM Boot Monitor or pre-loader is repeated once 30e62b008fSLinus Walleij * (to re-initialise any existing CM_INIT settings to safe values). 31e62b008fSLinus Walleij * 32e62b008fSLinus Walleij * This is usually not the desired behaviour since the platform 33e62b008fSLinus Walleij * will either reboot into the ARM monitor (or pre-loader) 34e62b008fSLinus Walleij * or continuously cycle thru it without U-Boot running, 35e62b008fSLinus Walleij * depending upon the setting of Integrator/CP switch S2-4. 36e62b008fSLinus Walleij * 37e62b008fSLinus Walleij * However it may be needed if Integrator/CP switch S2-1 38e62b008fSLinus Walleij * is set OFF to boot direct into U-Boot. 39e62b008fSLinus Walleij * In that case comment out the line below. 40e62b008fSLinus Walleij */ 41e62b008fSLinus Walleij #define CONFIG_CM_INIT 42e62b008fSLinus Walleij #define CONFIG_CM_REMAP 43e62b008fSLinus Walleij #define CONFIG_CM_SPD_DETECT 44e62b008fSLinus Walleij 45e62b008fSLinus Walleij /* 46e62b008fSLinus Walleij * The ARM boot monitor initializes the board. 47e62b008fSLinus Walleij * However, the default U-Boot code also performs the initialization. 48e62b008fSLinus Walleij * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT 49e62b008fSLinus Walleij * - see documentation supplied with board for details of how to choose the 50e62b008fSLinus Walleij * image to run at reset/power up 51e62b008fSLinus Walleij * e.g. whether the ARM Boot Monitor runs before U-Boot 52e62b008fSLinus Walleij */ 53e62b008fSLinus Walleij /* #define CONFIG_SKIP_LOWLEVEL_INIT */ 54e62b008fSLinus Walleij 55e62b008fSLinus Walleij /* 56e62b008fSLinus Walleij * The ARM boot monitor does not relocate U-Boot. 57e62b008fSLinus Walleij * However, the default U-Boot code performs the relocation check, 58e62b008fSLinus Walleij * and may relocate the code if the memory map is changed. 59e62b008fSLinus Walleij * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT 60e62b008fSLinus Walleij */ 61e62b008fSLinus Walleij /* #define SKIP_CONFIG_RELOCATE_UBOOT */ 62e62b008fSLinus Walleij 63e62b008fSLinus Walleij /* 64e62b008fSLinus Walleij * Physical Memory Map 65e62b008fSLinus Walleij */ 66e62b008fSLinus Walleij #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ 67e62b008fSLinus Walleij #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 68e62b008fSLinus Walleij #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 69e62b008fSLinus Walleij #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE 70e62b008fSLinus Walleij #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ 71e62b008fSLinus Walleij CONFIG_SYS_INIT_RAM_SIZE - \ 72e62b008fSLinus Walleij GENERATED_GBL_DATA_SIZE) 73e62b008fSLinus Walleij #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET 74a7b00a7bSLinus Walleij 75a7b00a7bSLinus Walleij /* 76a7b00a7bSLinus Walleij * FLASH and environment organization 77a7b00a7bSLinus Walleij * Top varies according to amount fitted 78a7b00a7bSLinus Walleij * Reserve top 4 blocks of flash 79a7b00a7bSLinus Walleij * - ARM Boot Monitor 80a7b00a7bSLinus Walleij * - Unused 81a7b00a7bSLinus Walleij * - SIB block 82a7b00a7bSLinus Walleij * - U-Boot environment 83a7b00a7bSLinus Walleij */ 84a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_BASE 0x24000000 85a7b00a7bSLinus Walleij #define CONFIG_SYS_MAX_FLASH_BANKS 1 86a7b00a7bSLinus Walleij 87a7b00a7bSLinus Walleij /* Timeout values in ticks */ 88a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ 89a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ 90a7b00a7bSLinus Walleij #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 91