1*88c307d1STim Harvey /* 2*88c307d1STim Harvey * Copyright (C) 2014 Gateworks Corporation 3*88c307d1STim Harvey * Author: Tim Harvey <tharvey@gateworks.com> 4*88c307d1STim Harvey * 5*88c307d1STim Harvey * SPDX-License-Identifier: GPL-2.0+ 6*88c307d1STim Harvey */ 7*88c307d1STim Harvey #ifndef __IMX6_SPL_CONFIG_H 8*88c307d1STim Harvey #define __IMX6_SPL_CONFIG_H 9*88c307d1STim Harvey 10*88c307d1STim Harvey #ifdef CONFIG_SPL 11*88c307d1STim Harvey 12*88c307d1STim Harvey #define CONFIG_SPL_FRAMEWORK 13*88c307d1STim Harvey 14*88c307d1STim Harvey /* 15*88c307d1STim Harvey * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: 16*88c307d1STim Harvey * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF 17*88c307d1STim Harvey * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well 18*88c307d1STim Harvey * - BOOT ROM stack is at 0x0091FFB8 19*88c307d1STim Harvey * - if icache/dcache is enabled (eFuse/strapping controlled) then the 20*88c307d1STim Harvey * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to 21*88c307d1STim Harvey * fit between 0x00907000 and 0x00918000. 22*88c307d1STim Harvey * - Additionally the BOOT ROM loads what they consider the firmware image 23*88c307d1STim Harvey * which consists of a 4K header in front of us that contains the IVT, DCD 24*88c307d1STim Harvey * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 25*88c307d1STim Harvey * or 64KB 26*88c307d1STim Harvey */ 27*88c307d1STim Harvey #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" 28*88c307d1STim Harvey #define CONFIG_SPL_TEXT_BASE 0x00908000 29*88c307d1STim Harvey #define CONFIG_SPL_MAX_SIZE (64 * 1024) 30*88c307d1STim Harvey #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" 31*88c307d1STim Harvey #define CONFIG_SPL_STACK 0x0091FFB8 32*88c307d1STim Harvey #define CONFIG_SPL_LIBCOMMON_SUPPORT 33*88c307d1STim Harvey #define CONFIG_SPL_LIBGENERIC_SUPPORT 34*88c307d1STim Harvey #define CONFIG_SPL_SERIAL_SUPPORT 35*88c307d1STim Harvey #define CONFIG_SPL_I2C_SUPPORT 36*88c307d1STim Harvey #define CONFIG_SPL_GPIO_SUPPORT 37*88c307d1STim Harvey 38*88c307d1STim Harvey /* NAND support */ 39*88c307d1STim Harvey #if defined(CONFIG_SPL_NAND_SUPPORT) 40*88c307d1STim Harvey #define CONFIG_SPL_NAND_MXS 41*88c307d1STim Harvey #define CONFIG_SPL_DMA_SUPPORT 42*88c307d1STim Harvey #endif 43*88c307d1STim Harvey 44*88c307d1STim Harvey /* MMC support */ 45*88c307d1STim Harvey #if defined(CONFIG_SPL_MMC_SUPPORT) 46*88c307d1STim Harvey #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */ 47*88c307d1STim Harvey #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 48*88c307d1STim Harvey #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 49*88c307d1STim Harvey #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) 50*88c307d1STim Harvey #endif 51*88c307d1STim Harvey 52*88c307d1STim Harvey /* SATA support */ 53*88c307d1STim Harvey #if defined(CONFIG_SPL_SATA_SUPPORT) 54*88c307d1STim Harvey #define CONFIG_SPL_SATA_BOOT_DEVICE 0 55*88c307d1STim Harvey #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 56*88c307d1STim Harvey #endif 57*88c307d1STim Harvey 58*88c307d1STim Harvey /* Define the payload for FAT/EXT support */ 59*88c307d1STim Harvey #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 60*88c307d1STim Harvey #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 61*88c307d1STim Harvey #define CONFIG_SPL_LIBDISK_SUPPORT 62*88c307d1STim Harvey #endif 63*88c307d1STim Harvey 64*88c307d1STim Harvey #define CONFIG_SPL_BSS_START_ADDR 0x18200000 65*88c307d1STim Harvey #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ 66*88c307d1STim Harvey #define CONFIG_SYS_SPL_MALLOC_START 0x18300000 67*88c307d1STim Harvey #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */ 68*88c307d1STim Harvey #define CONFIG_SYS_TEXT_BASE 0x17800000 69*88c307d1STim Harvey #endif 70*88c307d1STim Harvey 71*88c307d1STim Harvey #endif 72