188c307d1STim Harvey /* 288c307d1STim Harvey * Copyright (C) 2014 Gateworks Corporation 388c307d1STim Harvey * Author: Tim Harvey <tharvey@gateworks.com> 488c307d1STim Harvey * 588c307d1STim Harvey * SPDX-License-Identifier: GPL-2.0+ 688c307d1STim Harvey */ 788c307d1STim Harvey #ifndef __IMX6_SPL_CONFIG_H 888c307d1STim Harvey #define __IMX6_SPL_CONFIG_H 988c307d1STim Harvey 1088c307d1STim Harvey #ifdef CONFIG_SPL 1188c307d1STim Harvey 1288c307d1STim Harvey #define CONFIG_SPL_FRAMEWORK 1388c307d1STim Harvey 1488c307d1STim Harvey /* 1588c307d1STim Harvey * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: 1688c307d1STim Harvey * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF 1788c307d1STim Harvey * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well 1888c307d1STim Harvey * - BOOT ROM stack is at 0x0091FFB8 1988c307d1STim Harvey * - if icache/dcache is enabled (eFuse/strapping controlled) then the 2088c307d1STim Harvey * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to 2188c307d1STim Harvey * fit between 0x00907000 and 0x00918000. 2288c307d1STim Harvey * - Additionally the BOOT ROM loads what they consider the firmware image 2388c307d1STim Harvey * which consists of a 4K header in front of us that contains the IVT, DCD 2488c307d1STim Harvey * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 2588c307d1STim Harvey * or 64KB 2688c307d1STim Harvey */ 270351ef97SMarek Vasut #define CONFIG_SYS_THUMB_BUILD 2888c307d1STim Harvey #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" 2988c307d1STim Harvey #define CONFIG_SPL_TEXT_BASE 0x00908000 3088c307d1STim Harvey #define CONFIG_SPL_MAX_SIZE (64 * 1024) 3188c307d1STim Harvey #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" 3288c307d1STim Harvey #define CONFIG_SPL_STACK 0x0091FFB8 3388c307d1STim Harvey #define CONFIG_SPL_LIBCOMMON_SUPPORT 3488c307d1STim Harvey #define CONFIG_SPL_LIBGENERIC_SUPPORT 3588c307d1STim Harvey #define CONFIG_SPL_SERIAL_SUPPORT 3688c307d1STim Harvey #define CONFIG_SPL_I2C_SUPPORT 3788c307d1STim Harvey #define CONFIG_SPL_GPIO_SUPPORT 3888c307d1STim Harvey 3988c307d1STim Harvey /* NAND support */ 4088c307d1STim Harvey #if defined(CONFIG_SPL_NAND_SUPPORT) 4188c307d1STim Harvey #define CONFIG_SPL_NAND_MXS 4288c307d1STim Harvey #define CONFIG_SPL_DMA_SUPPORT 4388c307d1STim Harvey #endif 4488c307d1STim Harvey 4588c307d1STim Harvey /* MMC support */ 4688c307d1STim Harvey #if defined(CONFIG_SPL_MMC_SUPPORT) 4788c307d1STim Harvey #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */ 4888c307d1STim Harvey #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 49*205b4f33SGuillaume GARDET #define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1 5088c307d1STim Harvey #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) 5188c307d1STim Harvey #endif 5288c307d1STim Harvey 5388c307d1STim Harvey /* SATA support */ 5488c307d1STim Harvey #if defined(CONFIG_SPL_SATA_SUPPORT) 5588c307d1STim Harvey #define CONFIG_SPL_SATA_BOOT_DEVICE 0 5688c307d1STim Harvey #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 5788c307d1STim Harvey #endif 5888c307d1STim Harvey 5988c307d1STim Harvey /* Define the payload for FAT/EXT support */ 6088c307d1STim Harvey #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 61*205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 6288c307d1STim Harvey #define CONFIG_SPL_LIBDISK_SUPPORT 6388c307d1STim Harvey #endif 6488c307d1STim Harvey 6588c307d1STim Harvey #define CONFIG_SPL_BSS_START_ADDR 0x18200000 6688c307d1STim Harvey #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ 6788c307d1STim Harvey #define CONFIG_SYS_SPL_MALLOC_START 0x18300000 6888c307d1STim Harvey #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */ 6988c307d1STim Harvey #define CONFIG_SYS_TEXT_BASE 0x17800000 7088c307d1STim Harvey #endif 7188c307d1STim Harvey 7288c307d1STim Harvey #endif 73