1 /* 2 * Copyright (C) 2010 Heiko Schocher <hs@denx.de> 3 * 4 * based on: 5 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __IMX27LITE_COMMON_CONFIG_H 11 #define __IMX27LITE_COMMON_CONFIG_H 12 13 /* 14 * SoC Configuration 15 */ 16 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 17 #define CONFIG_MX27 18 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ 19 20 #define CONFIG_DISPLAY_BOARDINFO 21 #define CONFIG_DISPLAY_CPUINFO 22 23 #define CONFIG_SYS_TEXT_BASE 0xc0000000 24 25 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 26 #define CONFIG_SETUP_MEMORY_TAGS 1 27 #define CONFIG_INITRD_TAG 1 28 29 /* 30 * Lowlevel configuration 31 */ 32 #define SDRAM_ESDCFG_REGISTER_VAL(cas) \ 33 (ESDCFG_TRC(10) | \ 34 ESDCFG_TRCD(3) | \ 35 ESDCFG_TCAS(cas) | \ 36 ESDCFG_TRRD(1) | \ 37 ESDCFG_TRAS(5) | \ 38 ESDCFG_TWR | \ 39 ESDCFG_TMRD(2) | \ 40 ESDCFG_TRP(2) | \ 41 ESDCFG_TXP(3)) 42 43 #define SDRAM_ESDCTL_REGISTER_VAL \ 44 (ESDCTL_PRCT(0) | \ 45 ESDCTL_BL | \ 46 ESDCTL_PWDT(0) | \ 47 ESDCTL_SREFR(3) | \ 48 ESDCTL_DSIZ_32 | \ 49 ESDCTL_COL10 | \ 50 ESDCTL_ROW13 | \ 51 ESDCTL_SDE) 52 53 #define SDRAM_ALL_VAL 0xf00 54 55 #define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ 56 #define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 57 58 #define MPCTL0_VAL 0x1ef15d5 59 60 #define SPCTL0_VAL 0x043a1c09 61 62 #define CSCR_VAL 0x33f08107 63 64 #define PCDR0_VAL 0x120470c3 65 #define PCDR1_VAL 0x03030303 66 #define PCCR0_VAL 0xffffffff 67 #define PCCR1_VAL 0xfffffffc 68 69 #define AIPI1_PSR0_VAL 0x20040304 70 #define AIPI1_PSR1_VAL 0xdffbfcfb 71 #define AIPI2_PSR0_VAL 0x07ffc200 72 #define AIPI2_PSR1_VAL 0xffffffff 73 74 /* 75 * Memory Info 76 */ 77 /* malloc() len */ 78 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) 79 /* memtest start address */ 80 #define CONFIG_SYS_MEMTEST_START 0xA0000000 81 #define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ 82 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 83 #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ 84 #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ 85 86 /* 87 * Serial Driver info 88 */ 89 #define CONFIG_MXC_UART 90 #define CONFIG_MXC_UART_BASE UART1_BASE 91 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 92 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 93 94 /* 95 * Flash & Environment 96 */ 97 #define CONFIG_ENV_IS_IN_FLASH 98 #define CONFIG_FLASH_CFI_DRIVER 99 #define CONFIG_SYS_FLASH_CFI 100 /* Use buffered writes (~10x faster) */ 101 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 102 /* Use hardware sector protection */ 103 #define CONFIG_SYS_FLASH_PROTECTION 1 104 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 105 /* CS2 Base address */ 106 #define PHYS_FLASH_1 0xc0000000 107 /* Flash Base for U-Boot */ 108 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 109 #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ 110 CONFIG_SYS_FLASH_SECT_SZ) 111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 112 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ 113 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 114 /* Address and size of Redundant Environment Sector */ 115 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 116 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 117 118 /* 119 * Ethernet 120 */ 121 #define CONFIG_FEC_MXC 122 #define CONFIG_FEC_MXC_PHYADDR 0x1f 123 #define CONFIG_MII 124 125 /* 126 * MTD 127 */ 128 #define CONFIG_FLASH_CFI_MTD 129 #define CONFIG_MTD_DEVICE 130 131 /* 132 * NAND 133 */ 134 #define CONFIG_NAND_MXC 135 #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 137 #define CONFIG_SYS_NAND_BASE 0xd8000000 138 #define CONFIG_JFFS2_NAND 139 #define CONFIG_MXC_NAND_HWECC 140 141 /* 142 * SD/MMC 143 */ 144 #define CONFIG_MMC 145 #define CONFIG_GENERIC_MMC 146 #define CONFIG_MXC_MMC 147 #define CONFIG_DOS_PARTITION 148 149 /* 150 * GPIO 151 */ 152 #define CONFIG_MXC_GPIO 153 154 /* 155 * MTD partitions 156 */ 157 #define CONFIG_CMD_MTDPARTS 158 159 /* 160 * U-Boot general configuration 161 */ 162 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 163 /* Print buffer sz */ 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 165 sizeof(CONFIG_SYS_PROMPT) + 16) 166 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 167 /* Boot Argument Buffer Size */ 168 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 169 #define CONFIG_CMDLINE_EDITING 170 #define CONFIG_SYS_LONGHELP 171 172 /* 173 * U-Boot commands 174 */ 175 #include <config_cmd_default.h> 176 #define CONFIG_CMD_ASKENV 177 #define CONFIG_CMD_CACHE 178 #define CONFIG_CMD_DHCP 179 #define CONFIG_CMD_DIAG 180 #define CONFIG_CMD_FAT 181 #define CONFIG_CMD_JFFS2 182 #define CONFIG_CMD_MII 183 #define CONFIG_CMD_MMC 184 #define CONFIG_CMD_NAND 185 #define CONFIG_CMD_PING 186 187 #define CONFIG_BOOTDELAY 5 188 189 #define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ 190 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 191 192 #define CONFIG_EXTRA_ENV_SETTINGS \ 193 "netdev=eth0\0" \ 194 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 195 "nfsroot=${serverip}:${rootpath}\0" \ 196 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 197 "addip=setenv bootargs ${bootargs} " \ 198 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 199 ":${hostname}:${netdev}:off panic=1\0" \ 200 "addtty=setenv bootargs ${bootargs}" \ 201 " console=ttymxc0,${baudrate}\0" \ 202 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 203 "addmisc=setenv bootargs ${bootargs}\0" \ 204 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ 205 "kernel_addr_r=a0800000\0" \ 206 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 207 "rootpath=/opt/eldk-4.2-arm/arm\0" \ 208 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 209 "run nfsargs addip addtty addmtd addmisc;" \ 210 "bootm\0" \ 211 "bootcmd=run net_nfs\0" \ 212 "load=tftp ${loadaddr} ${u-boot}\0" \ 213 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 214 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 215 " +${filesize};cp.b ${fileaddr} " \ 216 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 217 "upd=run load update\0" \ 218 "mtdids=" MTDIDS_DEFAULT "\0" \ 219 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 220 221 /* additions for new relocation code, must be added to all boards */ 222 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 223 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 224 GENERATED_GBL_DATA_SIZE) 225 #endif /* __IMX27LITE_COMMON_CONFIG_H */ 226