1 /* 2 * Copyright (C) 2010 Heiko Schocher <hs@denx.de> 3 * 4 * based on: 5 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __IMX27LITE_COMMON_CONFIG_H 11 #define __IMX27LITE_COMMON_CONFIG_H 12 13 /* 14 * SoC Configuration 15 */ 16 #define CONFIG_ARM926EJS /* arm926ejs CPU core */ 17 #define CONFIG_MX27 18 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ 19 #define CONFIG_SYS_HZ 1000 20 21 #define CONFIG_DISPLAY_BOARDINFO 22 #define CONFIG_DISPLAY_CPUINFO 23 24 #define CONFIG_SYS_TEXT_BASE 0xc0000000 25 26 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 1 28 #define CONFIG_INITRD_TAG 1 29 30 /* 31 * Lowlevel configuration 32 */ 33 #define SDRAM_ESDCFG_REGISTER_VAL(cas) \ 34 (ESDCFG_TRC(10) | \ 35 ESDCFG_TRCD(3) | \ 36 ESDCFG_TCAS(cas) | \ 37 ESDCFG_TRRD(1) | \ 38 ESDCFG_TRAS(5) | \ 39 ESDCFG_TWR | \ 40 ESDCFG_TMRD(2) | \ 41 ESDCFG_TRP(2) | \ 42 ESDCFG_TXP(3)) 43 44 #define SDRAM_ESDCTL_REGISTER_VAL \ 45 (ESDCTL_PRCT(0) | \ 46 ESDCTL_BL | \ 47 ESDCTL_PWDT(0) | \ 48 ESDCTL_SREFR(3) | \ 49 ESDCTL_DSIZ_32 | \ 50 ESDCTL_COL10 | \ 51 ESDCTL_ROW13 | \ 52 ESDCTL_SDE) 53 54 #define SDRAM_ALL_VAL 0xf00 55 56 #define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ 57 #define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 58 59 #define MPCTL0_VAL 0x1ef15d5 60 61 #define SPCTL0_VAL 0x043a1c09 62 63 #define CSCR_VAL 0x33f08107 64 65 #define PCDR0_VAL 0x120470c3 66 #define PCDR1_VAL 0x03030303 67 #define PCCR0_VAL 0xffffffff 68 #define PCCR1_VAL 0xfffffffc 69 70 #define AIPI1_PSR0_VAL 0x20040304 71 #define AIPI1_PSR1_VAL 0xdffbfcfb 72 #define AIPI2_PSR0_VAL 0x07ffc200 73 #define AIPI2_PSR1_VAL 0xffffffff 74 75 /* 76 * Memory Info 77 */ 78 /* malloc() len */ 79 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) 80 /* memtest start address */ 81 #define CONFIG_SYS_MEMTEST_START 0xA0000000 82 #define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ 83 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 84 #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ 85 #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ 86 87 /* 88 * Serial Driver info 89 */ 90 #define CONFIG_MXC_UART 91 #define CONFIG_MXC_UART_BASE UART1_BASE 92 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 93 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 94 95 /* 96 * Flash & Environment 97 */ 98 #define CONFIG_ENV_IS_IN_FLASH 99 #define CONFIG_FLASH_CFI_DRIVER 100 #define CONFIG_SYS_FLASH_CFI 101 /* Use buffered writes (~10x faster) */ 102 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 103 /* Use hardware sector protection */ 104 #define CONFIG_SYS_FLASH_PROTECTION 1 105 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 106 /* CS2 Base address */ 107 #define PHYS_FLASH_1 0xc0000000 108 /* Flash Base for U-Boot */ 109 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 110 #define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ 111 CONFIG_SYS_FLASH_SECT_SZ) 112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 113 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ 114 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 115 /* Address and size of Redundant Environment Sector */ 116 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 117 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 118 119 /* 120 * Ethernet 121 */ 122 #define CONFIG_FEC_MXC 123 #define CONFIG_FEC_MXC_PHYADDR 0x1f 124 #define CONFIG_MII 125 126 /* 127 * MTD 128 */ 129 #define CONFIG_FLASH_CFI_MTD 130 #define CONFIG_MTD_DEVICE 131 132 /* 133 * NAND 134 */ 135 #define CONFIG_NAND_MXC 136 #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 137 #define CONFIG_SYS_MAX_NAND_DEVICE 1 138 #define CONFIG_SYS_NAND_BASE 0xd8000000 139 #define CONFIG_JFFS2_NAND 140 #define CONFIG_MXC_NAND_HWECC 141 142 /* 143 * SD/MMC 144 */ 145 #define CONFIG_MMC 146 #define CONFIG_GENERIC_MMC 147 #define CONFIG_MXC_MMC 148 #define CONFIG_DOS_PARTITION 149 150 /* 151 * GPIO 152 */ 153 #define CONFIG_MXC_GPIO 154 155 /* 156 * MTD partitions 157 */ 158 #define CONFIG_CMD_MTDPARTS 159 160 /* 161 * U-Boot general configuration 162 */ 163 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 164 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 165 /* Print buffer sz */ 166 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 167 sizeof(CONFIG_SYS_PROMPT) + 16) 168 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 169 /* Boot Argument Buffer Size */ 170 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 171 #define CONFIG_CMDLINE_EDITING 172 #define CONFIG_SYS_LONGHELP 173 174 /* 175 * U-Boot commands 176 */ 177 #include <config_cmd_default.h> 178 #define CONFIG_CMD_ASKENV 179 #define CONFIG_CMD_CACHE 180 #define CONFIG_CMD_DHCP 181 #define CONFIG_CMD_DIAG 182 #define CONFIG_CMD_FAT 183 #define CONFIG_CMD_JFFS2 184 #define CONFIG_CMD_MII 185 #define CONFIG_CMD_MMC 186 #define CONFIG_CMD_NAND 187 #define CONFIG_CMD_PING 188 189 #define CONFIG_BOOTDELAY 5 190 191 #define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ 192 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 193 194 #define CONFIG_EXTRA_ENV_SETTINGS \ 195 "netdev=eth0\0" \ 196 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 197 "nfsroot=${serverip}:${rootpath}\0" \ 198 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 199 "addip=setenv bootargs ${bootargs} " \ 200 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 201 ":${hostname}:${netdev}:off panic=1\0" \ 202 "addtty=setenv bootargs ${bootargs}" \ 203 " console=ttymxc0,${baudrate}\0" \ 204 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 205 "addmisc=setenv bootargs ${bootargs}\0" \ 206 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ 207 "kernel_addr_r=a0800000\0" \ 208 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 209 "rootpath=/opt/eldk-4.2-arm/arm\0" \ 210 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 211 "run nfsargs addip addtty addmtd addmisc;" \ 212 "bootm\0" \ 213 "bootcmd=run net_nfs\0" \ 214 "load=tftp ${loadaddr} ${u-boot}\0" \ 215 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 216 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 217 " +${filesize};cp.b ${fileaddr} " \ 218 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 219 "upd=run load update\0" \ 220 "mtdids=" MTDIDS_DEFAULT "\0" \ 221 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 222 223 /* additions for new relocation code, must be added to all boards */ 224 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 225 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ 226 GENERATED_GBL_DATA_SIZE) 227 #endif /* __IMX27LITE_COMMON_CONFIG_H */ 228